The Community for Technology Leaders
Quality Electronic Design, International Symposium on (2001)
San Jose, California
Mar. 26, 2001 to Mar. 28, 2001
ISBN: 0-7695-1025-6

Welcome Notes (PDF)

pp. xvi

ISQED Tutorials (PDF)

pp. null

Tutorial Track A (PDF)

pp. null
Tutorial A2: Design and Test of Low Voltage CMOS Circuits
Tutorial A3: Redundancy Requirements for Embedded Memories

Tutorial Track B (PDF)

pp. null
Tutorial B2: Fundamental Methods to Enable SoC Design and Reuse
Tutorial B3: Issues in Deep Submicron State-of-the-Art ESD Design

Tutorial Track C (PDF)

pp. null
Tutorial C2: Verification and Validation of Complex Digital Systems: An Industrial Perspective
Tutorial C3: Physical Verification at 0.13 Micron and Below

Tutorial Track D (PDF)

pp. null
Tutorial D1: Re-Connecting MOS Modeling and Circuit Design: New Methods for Design Quality
Tutorial D3: On-Chip Inductance Extraction and Modeling
Evening Panel Discussion: The 50-Million Transistor Chip: The Quality Challenge for 2001
Plenary Session I
Session 1A: Impact of Verification on Complex SOC Quality

Stopping Criteria Comparison: Towards High Quality Behavioral Verification (Abstract)

Isabelle Munn , Colorado State University
Amjad Hajjar , Colorado State University
Maria Bjorkman , Colorado State University
Tom Chen , Colorado State University
Anneliese Andrews , Colorado State University
pp. 31

Concrete Impact of Formal Verification on Quality in IP Design and Implementation (Abstract)

Andrea Fedeli , STMicroelectronics
Umberto Rossi , STMicroelectronics
Marco Boschini , STMicroelectronics
Franco Toto , STMicroelectronics
pp. 38

Simulation Using Code-Perturbation: Black- and White-Box Approach (Abstract)

Byeong Min , Texas A&M University
Zan Yang , Texas A&M University
Gwan Choi , Texas A&M University
pp. 44

A "Design for Verification" Methodology (Abstract)

M. Magnaghi , STMicroelectronics
A. Castelnuovo , STMicroelectronics
M. Brunelli , STMicroelectronics
L. Battù , STMicroelectronics
F. Sforza , STMicroelectronics
pp. 50
Session 1B: Quality of EDA Tools and Design Methodologies

I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os (Abstract)

Charles Chiu , IBM Microelectronics Division
Robert A. Proctor , IBM Microelectronics Division
Gulsun Yasar , IBM Microelectronics Division
James P. Libous , IBM Microelectronics Division
pp. 71

Scripting for EDA Tools: A Case Study (Abstract)

Kurt Keutzer , U.C. Berkeley
Pinhong Chen , U.C. Berkeley
pp. 87
Session 1C: Design, Fabrication and Reliability Challenges for Emerging Technologies

High Quality Analog CMOS and Mixed Signal LSI Design (Abstract)

Akira Matsuzawa , Matsushita Electric Industrial Co., Ltd.
pp. 97

CAD Issues for CMOS VLSI Design in SOI (Abstract)

Kenneth L. Shepard , Columbia University and CadMOS Design Technlogy
pp. 105

Foundry's Perspective of System Integration: Quality Design and Time-to-Volume (Abstract)

Fred Wang , Taiwan Semiconductor Manufacturing Company
Lie-Szu Juang , Taiwan Semiconductor Manufacturing Company
Sheldon Wu , Taiwan Semiconductor Manufacturing Company
pp. 111

Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications (Abstract)

Robert W. Dutton , Stanford University
Choshu Ito , Stanford University
Kaustav Banerjee , Stanford University
pp. 117
Session 2A: Capacitive Crosstalk Analysis

Noise Model for Multiple Segmented Coupled RC Interconnects (Abstract)

Niranjan Pol , Cadence Design Systems, Inc.
Andrew B. Kahng , UCSD CSE and ECE Departments
Devendra Vidhani , SUN Microsystems, Inc.
Sudhakar Muddu , Sanera Systems, Inc.
pp. 145

New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees (Abstract)

Qingjian Yu , Univ. of California at Berkeley
Ernest S. Kuh , Univ. of California at Berkeley
pp. 151

A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance (Abstract)

David Blaauw , Motorola Inc.
Chanhee Oh , Motorola Inc.
Supamas Sirichotiyakul , Motorola Inc.
Rafi Levy , Motorola Semiconductor Israel Ltd.
Jingyan Zuo , Motorola Inc.
Murat R. Becer , Motorola Inc.
Vladimir Zolotov , Motorola Inc.
Ibrahim N. Hajj , University of Illinois at Urbana-Champaign
pp. 158
Session 2B: Interconnect Modeling and Analysis

Computational Cost Reduction in Extracting Inductance (Abstract)

Kunihiro Asada , The University of Tokyo
Makoto Ikeda , The University of Tokyo
Yusuke Nakashima , The University of Tokyo
pp. 179

Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion (Abstract)

Xuejue Huang , University of California, at Berkeley
Yu Cao , University of California, at Berkeley
O. Sam Nakagawa , Hewlett-Packard Laboratories
Chenming Hu , University of California, at Berkeley
Shen Lin , Hewlett-Packard Laboratories
Norman Chang , Hewlett-Packard Laboratories
Weize Xie , Hewlett-Packard Laboratories
pp. 185
Session 2C: Power-Aware Design

Memory Bus Encoding for Low Power: A Tutorial (Abstract)

Massoud Pedram , University of Southern California
Wei-Chung Cheng , University of Southern California
pp. 199

RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits (Abstract)

G. Bai , University of Illinois at Urbana-Champaign
S. Bobba , University of Illinois at Urbana-Champaign
I.N. Hajj , University of Illinois at Urbana-Champaign
pp. 205

Instruction Prediction for Step Power Reduction (Abstract)

Shen Lin , Hewlett-Packard Laboratories
Weize Xie , Hewlett-Packard Laboratories
Sam Nakagawa , Hewlett-Packard Laboratories
Zhenyu Tang , Univ. of Wisconsin
Lei He , Univ. of Wisconsin
Norman Chang , Hewlett-Packard Laboratories
pp. 211

A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits (Abstract)

J.A. Montiel-Nelson , University of Las Palmas de Gran Canaria.
And A. Nunez , University of Las Palmas de Gran Canaria.
R. Sarmiento , University of Las Palmas de Gran Canaria.
V de ARMAS , University of Las Palmas de Gran Canaria.
pp. 223
Evening Panel Discussion: 0.13 micron: Will the Speed Bumps Slow the Race to Market?
Plenary Session II
Session D: Ph.D. Student Forum
Session E: Poster Session

Constructive Floorplanning with a Yield Objective (Abstract)

Rajnish Prasad , University of Massachusetts
Israel Koren , University of Massachusetts
pp. 261

Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process (Abstract)

M.-C. Wang , United Microelectronics Corporation (UMC)
Wen-Yu Lo , National Chiao-Tung University,
S.-S. Chen , United Microelectronics Corporation (UMC)
Tung-Yang Chen , National Chiao-Tung University,
Howard Tang , United Microelectronics Corporation (UMC)
Ming-Dou Ker , National Chiao-Tung University,
pp. 267

VSIA Quality Metrics for IP and SoC (Abstract)

Charlene C. Johnson , Intel Corp.
Mark Birnbaum , Fujitsu Microelectronics, Inc.
pp. 279

Hot-carrier-Induced Circuit Degradation for 0.18 μm CMOS Technology (Abstract)

A.S. Oates , Bell Laboratories
Yuan Chen , Bell Laboratories
Joshua McConkey , University of Central Florida
Qiang Li , University of Central Florida
J.S. Yuan , University of Central Florida
Jonathan Zhou , Bell Laboratories
Sundar Chetlur , Bell Laboratories
Wei Li , University of Central Florida
pp. 284

Verification of Embedded Phase-Locked Loops (Abstract)

Tom Egan , Santa Clara University
Samiha Mourad , Santa Clara University
pp. 290

HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis (Abstract)

Yi-Min Jiang , Synopsys, Inc.
Kwang-Ting (Tim) Cheng , University of California at Santa Barbara
Han Young Koh , LightSpeed Semiconductor Corp.
pp. 307

Energy Efficient Signaling in Deep Submicron CMOS Technology (Abstract)

Hannu Tenhunen , Royal Institute of Technology
Imed Ben Dhaou , Royal Institute of Technology
Vijay Sundararajan , University of Minnesota
Keshab K. Parhi , University of Minnesota
pp. 319

Complex Reliability Evaluation of Voters for Fault Tolerant Designs (Abstract)

Radu Munteanu , Technical University of Cluj-Napoca
Mihaela Radu , Technical University of Cluj-Napoca
Dan Pitica , Technical University of Cluj-Napoca
Cristian Posteuca , Technical University of Cluj-Napoca
pp. 331

Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow (Abstract)

Josef Schmid , Lucent Technologies Network Systems
Timo Schüring , Lucent Technologies Network Systems
Christoph Smalla , Lucent Technologies Network Systems
pp. 337

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths (Abstract)

Y. Zorian , LogicVision
D. Gizopoulos , University of Piraeus
M. Psarakis , NCSR "Demokritos"
A. Paschalis , University of Athens
N. Kranitis , NCSR "Demokritos"
pp. 343

On Accumulator-Based Bit-Serial Test Response Compaction Schemes (Abstract)

D. Nikolos , Computer Technology Institute
X. Kavousianos , University of Patras
D. Bakalis , Computer Technology Institute
H. T. Vergos , Computer Technology Institute
pp. 350
Session 3A: Defect Analysis and Test Generation

Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects (Abstract)

M. Renovell , Universit? de Montpellier II: Sciences et Techniques du Languedoc
pp. 359

Defect-Oriented Fault Simulation and Test Generation in Digital Circuits (Abstract)

W. Kuzmicz , Warsaw University of Technology
W. Pleskacz , Warsaw University of Technology
J. Raik , Tallinn Technical University
R. Ubar , Tallinn Technical University
pp. 365

Automatic Functional Vector Generation Using the Interacting FSM Model (Abstract)

Chia-Chih Yen , National Chiao Tung University
Jing-Yang Jou , National Chiao Tung University
Chien-Nan Jimmy Liu , National Chiao Tung University
pp. 372

Color Counting and its Application to Path Delay Fault Coverage (Abstract)

Spyros Tragoudas , Southern Illinois University at Carbondale
Jayant Deodhar , Intel Corporation
pp. 378

ATPG for Path Delay Faults without Path Enumeration (Abstract)

M. Michael , Southern Illinois University
S. Tragoudas , Southern Illinois University
pp. 384
Session 3B: Design of Programmable and Platform-Based IP

HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec (Abstract)

Albert Van der Werf , Philips Research Laboratories
Steffen Maul , Philips Research Laboratories
Marcel Oosterhuis , Philips Research Laboratories
Paul Lippens , Philips Research Laboratories
Jim Lin , Philips Research Laboratories
Sethuraman Ramanathan , Philips Research Laboratories
Rafael Peset Llopis , Philips Research Laboratories
pp. 393

Acceleration of DAB Chipset Development by Deployment of a Real-time Rapid Prototyping Approach based on Behavioral Synthesis (Abstract)

Martin Leyh , Fraunhofer Institute for Integrated Circuits
Martin Speitel , Fraunhofer Institute for Integrated Circuits
Michael Schlicht , Fraunhofer Institute for Integrated Circuits
pp. 399

ELITE Design Methodology of Foundation IP for Improving Synthesis Quality (Abstract)

Chih-Yuan Chen , Industrial Technology Research Institute
Shing-Wu Tung , Industrial Technology Research Institute
pp. 405

Implementation of Multipliers in FPGA Structures (Abstract)

Ernest Jamro , AGH Technical University of Cracow
Kazimierz Wiatr , AGH Technical University of Cracow
pp. 415
Session 3C: Embedded Panel Discussion: Consequences of Technology: What is the Impact of Electronic Design on the Quality of Life?
Session 4A: Design for Manufacturability

Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations (Abstract)

Lawrence T. Pileggi , Carnegie Mellon Univ.
Emrah Acar , Carnegie Mellon Univ.
Sani Nassif , IBM-Austin Research Labs
Ying Liu , IBM-Austin Research Labs
pp. 431

Timing Yield Estimation from Static Timing Analysis (Abstract)

Chris Long , Sematech
Anne Gattiker , IBM Austin Research Lab
Rashmi Dinakar , Rensselaer Polytechnic Institute
Sani Nassif , IBM Austin Research Lab
pp. 437

Performance Improvement for High Speed Devices Using E-tests and the SPICE Model (Abstract)

Young-Kwan Park , SAMSUNG Electronics Co., Ltd.
Tae-Seon Kim , SAMSUNG Electronics Co., Ltd.
Sang-Hoon Lee , SAMSUNG Electronics Co., Ltd.
Hoe-Jin Lee , SAMSUNG Electronics Co., Ltd.
Taek-Soo Kim , SAMSUNG Electronics Co., Ltd.
Seok-Jin Kim , SAMSUNG Electronics Co., Ltd.
Tae-Jin Kwon , SAMSUNG Electronics Co., Ltd.
Jeong-Taek Kong , SAMSUNG Electronics Co., Ltd.
pp. 443
Session 4B: Embedded Memories

A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies (Abstract)

M. Morbarigazzi , STMicroelectronics N.V.
C. Roma , STMicroelectronics N.V.
P. Daglio , STMicroelectronics N.V.
M. Araldi , STMicroelectronics N.V.
pp. 451

Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1 (Abstract)

D. Soudris , Democritus University of Thrace
A. Argyriou , Democritus University of Thrace
K. Tatas , Democritus University of Thrace
M. Dasigenis , Democritus University of Thrace
N. Zervas , University of Patras
pp. 456

A Method of Embedded Memory Access Time Measurement (Abstract)

Tsung-Yi Wu , Taiwan Semiconductor Manufacturing Company Ltd.
Nai-Yin Sung , Taiwan Semiconductor Manufacturing Company Ltd.
pp. 462
Session 4C: Device Modeling and Design Quality

Noise in Radio Frequency Circuits: Analysis and Design Implications (Abstract)

Amit Mehrotra , University of Illinois at Urbana Champaign
pp. 469

Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation (Abstract)

Takafumi Ohmoto , Hiroshima University
Makoto Nagata , Hiroshima University
Takashi Morie , Hiroshima University
Atsushi Iwata , Hiroshima University
Yoshitaka Murasaka , Hiroshima University
pp. 482

Modeling of Substrate Noise Injected by Digital Libraries (Abstract)

Edoardo Charbon , Cadence Design Systems Inc.
Paolo Miliozzi , Conexant Systems Inc.
Stefano Zanella , Universita degli Studi di Padova
Enrico Zanoni , Universita degli Studi di Padova
Luca Carloni , University of California Berkeley
Andrea Neviani , Universita degli Studi di Padova
Alberto Sangiovanni-Vincentelli , University of California Berkeley
Carlo Guardiani , PDF Solutions Inc.
pp. 488

Author Index (PDF)

pp. 493
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