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Quality Electronic Design, International Symposium on (2001)
San Jose, California
Mar. 26, 2001 to Mar. 28, 2001
ISBN: 0-7695-1025-6
pp: 284
Wei Li , University of Central Florida
Qiang Li , University of Central Florida
J.S. Yuan , University of Central Florida
Joshua McConkey , University of Central Florida
Yuan Chen , Bell Laboratories
Sundar Chetlur , Bell Laboratories
Jonathan Zhou , Bell Laboratories
A.S. Oates , Bell Laboratories
ABSTRACT
Because the supply voltage is not proportional scaled with the device size, the further scaling down of CMOS devices is in turn accompanied with more and more severe hot-carrier reliability problems. Hot-carriers, the high energy carriers due to high electric field in the channel, are injected into the gate oxide or cause trapping states generation between Si and SiO2 interface, which is accumulated and cause long run reliability problems in devices and circuits. In this paper, we describe a systematic method to evaluate the circuit degradation due to hot-carrier stressing. First the substrate current and gate leakage current models are improved for more accuracy in predicting the lifetime of the devices and circuits. The hot-carrier stressing characterization is carried out for 0.18 μm technology. The circuit performance degradation is then evaluated using the parameters extracted from 0.18 μm technology for both digital logic circuits and RF circuits.
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CITATION

A. Oates et al., "Hot-carrier-Induced Circuit Degradation for 0.18 μm CMOS Technology," Quality Electronic Design, International Symposium on(ISQED), San Jose, California, 2001, pp. 284.
doi:10.1109/ISQED.2001.915244
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