The Community for Technology Leaders
Quality Electronic Design, International Symposium on (2001)
San Jose, California
Mar. 26, 2001 to Mar. 28, 2001
ISBN: 0-7695-1025-6
pp: 185
Yu Cao , University of California, at Berkeley
Xuejue Huang , University of California, at Berkeley
Chenming Hu , University of California, at Berkeley
Norman Chang , Hewlett-Packard Laboratories
Shen Lin , Hewlett-Packard Laboratories
O. Sam Nakagawa , Hewlett-Packard Laboratories
Weize Xie , Hewlett-Packard Laboratories
ABSTRACT
A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (Leff) for multiple lines. Based on look-up table for Leff, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlist for multiple lines, this approach greatly improves the computation efficiency and maintains accuracy for timing and signal integrity analysis. Applications to repeater insertion in the critical path chains are demonstrated. For a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC multiple line models.
INDEX TERMS
CITATION

X. Huang et al., "Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion," Quality Electronic Design, International Symposium on(ISQED), San Jose, California, 2001, pp. 185.
doi:10.1109/ISQED.2001.915225
97 ms
(Ver 3.3 (11022016))