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Quality Electronic Design, International Symposium on (2000)
San Jose, California
Mar. 20, 2000 to Mar. 22, 2000
ISBN: 0-7695-0525-2
Tutorial Track 1: Design for Reliability and Manufacturability: Organizer and Moderator: Ibrahim Hajj

ISQED Tutorials (Abstract)

Ibrahim Hajj , University of Illinois at Urbana-Champaign
pp. 5
Tutorial Track II: Design for Reliability and Manufacturability: Organizer and Moderator: Ali Iramanesh
Tutorial Track III: Closing the Manufacturing Loop: Organizer and Moderator: Andrzej Strojwas
Evening Panel Discussion

How Do You Select A High Quality EDA Tool Flow? (Abstract)

Robert N. Blair , RNB International
Jacques Benkoski , Monterey Design Systems
pp. 17
Plenary Session I: Session Chair: Ali Iramanesh

Slap it Together and Ship it! (Abstract)

Aart J. de Geus , Synopsys Inc.
pp. 23

The Practical Side of Quality (Abstract)

John East , Actel Corporation
pp. 25
Session 1A: Panel Discussion
Session 1B: DSM Modeling: Organizers: Ann Spratt and Antonio Nunez: Co-Chairs: Resve Saleh and Antonio Nunez

Transistor Modeling for the VDSM Era (Abstract)

Michael S. Shur , Rensselaer Polytechnic Institute
Tor A. Fjeldly , Norwegian University of Science and Technology
Trond Ytterdal , Nordic VLSI
pp. 37

A Statistical Model for Electromigration Failures (Abstract)

Gilbert Yoh , Agilent Technologies
Farid N. Najm , University of Toronto
pp. 45

An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling (Abstract)

Murat R Becer , University of Illinois at Urbana-Champaign
Ibrahim N. Hajj , University of Illinois at Urbana-Champaign
pp. 51

Power Macromodeling for a High Quality RT-Level Power Estimation (Abstract)

R. Zafalon , STMicroelectronics
M. Rossello , STMicroelectronics
E. Macii , STMicroelectronics
M. Poncino , STMicroelectronics
pp. 59
Session 1C: Emerging Process and Device Technology: Organizers: David Overhauser and Chune-Sin Yeh: Co-Chairs: David Overhauser and Chune-Sin Yeh

Overview of SiGe Technology Modeling and Application (Abstract)

Jiann S. Yuan , University of Central Florida
pp. 67

GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design (Abstract)

Lifeng Wu , BTA Technology Inc.
Jingkun Fang , BTA Technology Inc.
Heting Yan , BTA Technology Inc.
Ping Chen , BTA Technology Inc.
Alvin I-Hsien Chen , BTA Technology Inc.
Yoshifumi Okamoto , BTA Technology Inc.
Chune-Sin Yeh , BTA Technology Inc.
Zhihong Liu , BTA Technology Inc.
Nobufusa Iwanishi , Matsushita Electronics Co.
Norio Koike Hirokazu Yonezawa , Matsushita Electronics Co.
Yoshiyuki Kawakami , Matsushita Electronics Co.
pp. 73

An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18?m ASIC (Abstract)

Ji-Soong Park , Samsung Electronics Co., Ltd.
Chul-Hong Park , Samsung Electronics Co., Ltd.
Sang-Uhk Rhie , Samsung Electronics Co., Ltd.
Yoo-Hyon Kim , Samsung Electronics Co., Ltd.
Moon-Hyun Yoo , Samsung Electronics Co., Ltd.
Jeong-Taek Kong , Samsung Electronics Co., Ltd.
Hyung-Woo Kim , ASIC TD(Technology Development)
Sun-Il Yoo , ASIC TD(Technology Development)
pp. 81

Three Dimensional Analysis of Thermal Degradation Effects in FDSOI MOSFET's (Abstract)

Kwan-Do Kim , CAE, Semiconductor
Young-Kwan Park , CAE, Semiconductor
Jun-Ha Lee , CAE, Semiconductor
Jeong-Taek Kong , CAE, Semiconductor
Hee-Sung Kang , Samsung Electronics Co., Ltd.
Young-Wug Kim , Samsung Electronics Co., Ltd.
Seok-Jin Kim , Samsung Electronics Co., Ltd.
pp. 87
Session 2A: Quality of Design and EDA Tools: Organizer: George Alexiou and Ali Iramanesh: Co-Chairs: George Alexiou and Kevin Lashkari

Quality-Driven System-on-a-Chip Design (Abstract)

Lech Józwiak , Eindhoven University of Technology
pp. 93

Advancing Customer-Perceived Quality in the EDA Industry (Abstract)

Giora Ben-Yaacov , Synopsys, Inc.
Larry Bjork , Synopsys, Inc.
Edward P. Stone , Synopsys, Inc.
pp. 411

Quality Memory Blocks ? Balancing the Trade-Offs (Abstract)

Betty Prince , Memory Strategies International
pp. 109

Should Yield be a Design Objective? (Abstract)

Israel Koren , University of Massachusetts at Amherst
pp. 115

Early Addressing IC and Package Relationship Allows an Overall Better Quality of Complex SOC (Abstract)

Anna Fontanelli , STMicroelectronics
Luigi Arnone , STMicroelectronics
Roberto Branca , STMicroelectronics
Giorgio Mastrorocco , STMicroelectronics
pp. 121
Session 2B: Emerging Integrity Issues: Organizer: Tak Young and Marco Casale-Rossi: Co-Chairs: Marco Casale-Rossi and Norman Chang

LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator (Abstract)

Kenji Shimazaki , Matsushita Electric Industrial Co., Ltd.
Hiroyuki Tsujikawa , Matsushita Electric Industrial Co., Ltd.
Seijiro Kojima , Matsushita Electric Industrial Co., Ltd.
Shouzou Hirano , Matsushita Electric Industrial Co., Ltd.
pp. 129

Dynamic Timing Analysis Considering Power Supply Noise Effects (Abstract)

Yi-Min Jiang , Synopsys, Inc.
Angela Krstic , University of California at Santa Barbara
Kwang-Ting (Tim) Cheng , University of California at Santa Barbara
pp. 137

Full Chip Thermal Simulation (Abstract)

Zhiping Yu , Stanford University and Hewlett Packard Co.
Dan Yergeau , Stanford University
Robert W. Dutton , Stanford University
Sam Nakagawa , Hewlett Packard Co.
Norman Chang , Hewlett Packard Co.
Shen Lin , Hewlett Packard Co.
Weize Xie , Hewlett Packard Co.
pp. 145

Enabling DIR(Designing-In-Reliability) through CAD Capabilities (Abstract)

Wonjae Kang , Intel
Brad Potts , Advanced Micro Devices
Ray Hokinson , Compaq
John Riley , Lucent Technologies
David Doman , Motorola
Frank Cano , Texas Instruments
N.S. Nagaraj , Texas Instruments
Noel Durrant , SEMATECH
pp. 151

Noise Safety Design Methodologies (Abstract)

M. Graziano , Politecnico di Torino
M. Delaurenti , Politecnico di Torino
G. Masera , Politecnico di Torino
G. Piccinini , Politecnico di Torino
M. Zamboni , Politecnico di Torino
pp. 157
Session 2C: Low Power Test: Organizers: Fadi Maamari, Marcel Jacomet, Kaushik Roy, Anne-Marie Trullemans, Ibramham Hajj and Raimund Ubar: Co-Chairs: Marcel Jacomet and Ibrahim Hajj

Low Power Testing of VLSI Circuits: Problems and Solutions (Abstract)

Patrick Girard , Universit? Montpellier II / CNRS
pp. 173

Efficient Hierarchical Approach to Test Generation for Digital Systems (Abstract)

Raimund Ubar , Tallinn Technical University
Jaan Raik , Tallinn Technical University
pp. 189

Quality of Electronic Design: From Architectural Level to Test Coverage (Abstract)

O.P. Dias , Escola Superior de Tecnologia/IPS
J. Semião , Escola Superior de Tecnologia/UA
M.B. Santos , Instituto Superior T?cnico/UTL
I.M. Teixeira , Instituto Superior T?cnico/UTL
J.P. Teixeira , Instituto Superior T?cnico/UTL
pp. 197
Evening Panel Discussion
Plenary Session II: Co-Chairs: Resve Saleh and Carlo Guardiani

Embedded-Quality for Test (Abstract)

Yervant Zorian , LogicVision
pp. 211
Session 3A: Quality of IP Blocks: Organizers: Ann Spratt and Antonio N??ez: Co-Chairs: Fadi Maamari and Robert Aitken

An Objective Measure of Digital System Design Quality (Abstract)

Dave Protheroe , South Bank University
Francesco Pessolano , South Bank University
pp. 227

Achieving the Quality of Verification for Behavioral Models with Minimum Effort (Abstract)

Tom Chen , Colorado State University
Anneliese von Mayrhauser , Colorado State University
Amjad Hajjar , Colorado State University
Charles Anderson , Colorado State University
Mehmet Sahinoglu , Troy State University Montgomry
pp. 234
Session 3B: Impact of Emerging Processes on Design Quality: Organizer: Kris Verma: Co-Chairs: Kris Verma and NS Nagaraj

Combining Advanced Process Technology and Design for Systems Level Integration (Abstract)

Ana Hunter , Chartered Semiconductor Manufacturing Ltd
Ck Lau , Chartered Semiconductor Manufacturing Ltd
John Martin , Chartered Semiconductor Manufacturing Ltd
pp. 245
Session 3C: Poster Session: Co-Chairs: Norman Chang and C.K. Cheng

Power Bus Maximum Voltage Drop in Digital VLSI Circuits (Abstract)

G. Bai , University of Illinois at Urbana-Champaign
S. Bobba , University of Illinois at Urbana-Champaign
I.N. Hajj , University of Illinois at Urbana-Champaign
pp. 263

A Reliable Clock Tree Design Methodology for ASIC Designs (Abstract)

Mely Chen Chi , Chung Yuan Christian University
Shih-Hsu Huang , Industrial Technology Research Institutes
pp. 269

Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion (Abstract)

Peter H. Chen , TeraLogic Incorporated
Sunil Malkani , TeraLogic Incorporated
Chun-Mou Peng , International Technical University
James Lin , National Semiconductor Corp.
pp. 275

On Testability of Multiple Precharged Domino Logic (Abstract)

Th. Haniotakis , LSD S. A.
Y. Tsiatouhas , LSD S. A.
D. Nikolos , University of Patras
C. Efstathiou , TEI of Athens
pp. 299

DVDT: Design for Voltage Drop Test Using Onchip-Voltage Scan Path (Abstract)

Makoto Ikeda , University of Tokyo
Hideyuki Aoki , University of Tokyo
Kunihiro Asada , University of Tokyo
pp. 305

A Reconfigurable Low-Power High-Performance Matrix Multiplier Design (Abstract)

Rong Lin , State University of New York at Geneseo
pp. 321

Correct-by-Design CAD Enhancement for EMI Signal Integrity (Abstract)

Erik A. McShane , University of Illinois at Chicago
Krishna Shenai , University of Illinois at Chicago
pp. 341

A Transition Based BIST Approach for Passive Analog Circuits (Abstract)

Alvernon Walker , University of Tennessee
Parag K. Lala , University of Arkansas
pp. 347

Aliasing-Free Space and Time Compactions with Limited Overhead (Abstract)

Jin Ding , Silicon Systems Limited
David Moloney , Silicon Systems Limited
Xiaojun Wang , Dublin City University
pp. 355

A Pre-Simulation Measure of D.C. Design-for-Testability Fault Diagnosis Quality (Abstract)

Matthew Worsman , Hong Kong Polytechnic University
Mike W.T. Wong , Hong Kong Polytechnic University
Y.S. Lee , Hong Kong Polytechnic University
pp. 361

An Automated Shielding Algorithm and Tool For Dynamic Circuits (Abstract)

Gin S. Yee , University of Washington and Sun Microsystems Incorporated
Tyler Thorp , University of Washington and Sun Microsystems Incorporated
Ron Christopherson , Sun Microsystems Incorporated
Ban P. Wang , Sun Microsystems Incorporated
Carl Sechen , University of Washington
pp. 369

A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect Impedance (Abstract)

Li-Fu Chang , Frequency Technology, Inc.
Keh-Jeng Chang , Frequency Technology, Inc.
Christophe Bianchi , Frequency Technology, Inc.
pp. 375
Session 4A: Panel Discussion

Focus on Quality of Design: Does it Help or Hinder Time to Market? (Abstract)

Nader Vasseghi , Sebring Systems Incorporated
Rita Glover , EDA today
pp. 383
Session 4B: Quality Definitions and Metrics: Organizers: George Alexiou and Ali Iramanesh: Co-Chairs: Justin Harlow and Lei He

Quality of EDA CAD Tools: Definitions, Metrics and Directions (Abstract)

A.H. Farrahi , IBM T.J. Watson Research Center
D.J. Hathaway , IBM Electronic Design Automation
M. Wang , Northwestern University
M. Sarrafzadeh , Northwestern University
pp. 395

Tool Interoperability is Key to Improved Design Quality (Abstract)

Richard Goldman , Synopsys Incorporated
Karen Bartleson , Synopsys Incorporated
pp. 407
Session 4C: Low Power Design and Test: Organizers: Fadi Maamari, Marcel Jacomet, Kaushik Roy, Anne-Marie Trullemans and Ibramham Hajj: Co-Chairs: Kaushik Roy and Vamsi K. Srikantam

Peak Power Reduction in Low Power BIST (Abstract)

Xiaodong Zhang , Purdue University
Kaushik Roy , Purdue University
pp. 425

Low Power BIST for Wallace Tree-Based Fast Multipliers (Abstract)

D. Bakalis , University of Patras and Computer Technology Institute
D. Nikolos , University of Patras and Computer Technology Institute
G. Alexiou , University of Patras and Computer Technology Institute
E. Kalligeros , University of Patras
H.T. Vergos , University of Patras
pp. 433

Probabilistic Bottom-Up RTL Power Estimation (Abstract)

Ricardo Ferreira , Universite Catholique de Louvain
A-M. Trullemans , Universite Catholique de Louvain
Jose Costa , Instituto Superior Tecnico
Jose Monteiro , Instituto Superior Tecnico
pp. 439
Session 5A: Panel Discussion
Session 5B: Design for Manufacturability: Organizers: Andrzej J. Strojwas and Carlo Guardiani: Co-Chairs: Glendy Sun and Vinod Malhotra

Design for Variability in DSM Technologies (Abstract)

Sani R. Nassif , IBM Austin Research Laboratory
pp. 451

Realistic Worst-Case Modeling by Performance Level Principal Component Analysis (Abstract)

Alessandra Nardi , Universit? di Padova
Andrea Neviani , Universit? di Padova
Carlo Guardiani , PDF Solutions Incorporated
pp. 455

Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs (Abstract)

V. Axelrad , SEQUOIA Design Systems
N. Cobb , Mentor Graphics
M. O'Brien , Mentor Graphics
T. Do , Mentor Graphics
T. Donnelly , Mentor Graphics
Y. Granik , Mentor Graphics
E. Sahouria , Mentor Graphics
V. Boksha , Massachusetts Institute of Technology
A. Balasinski , Cypress Semiconductor
pp. 461

Electronic Process Limited Yield (Abstract)

Gary W. Maier , IBM Corporation
Shawn Smith , Knights Technology Incorporated
pp. 467

Effects of Package Stackups on Microprocessor Performance (Abstract)

Mehdi M. Mechaik , CAE Software Engineer & PCB Design
pp. 475
Session 5C: VDSM Capacitive and Inductive Issues: Organizers: Tak Young and Marco Casale-Rossi: Co-Chairs: Tak Young and Eileen Hong You

Coupling Noise Analysis for VLIS and ULSI Circuits (Abstract)

Kathirgamar Aingaran , Sun Microsystems Inc.
Fabian Klass , Sun Microsystems Inc.
Chin-Man Kim , Sun Microsystems Inc.
Chaim Amir , Sun Microsystems Inc.
Joydeep Mitra , Sun Microsystems Inc.
Eileen You , Sun Microsystems Inc.
Jamil Mohd , Sun Microsystems Inc.
Sai-Keung Dong , Sun Microsystems Inc.
pp. 485

Efficient Delay Calculation in Presence of Crosstalk (Abstract)

Tong Xiao , University of California at Santa Barbara
Malgorzata Marek-Sadowska , University of California at Santa Barbara
pp. 491

Crosstalk Aware Static Timing Analysis: A Two Step Approach (Abstract)

B. Franzini , STMicroelectronics
C. Forzan , STMicroelectronics
D. Pandini , STMicroelectronics
P. Scandolara , STMicroelectronics
A. Dal Fabbro , STMicroelectronics
pp. 499

Quick On-Chip Self- and Mutual-Inductance Screen (Abstract)

Shen Lin , Hewlett-Packard Laboratories
Norman Chang , Hewlett-Packard Laboratories
Sam Nakagawa , Hewlett-Packard Laboratories
pp. 513

Organizations Index (Abstract)

pp. 521

Author Index (PDF)

pp. 523
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