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2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (2014)
CA, USA
March 23, 2014 to March 25, 2014
ISBN: 978-1-4799-3604-5
TABLE OF CONTENTS

Title page (PDF)

pp. c1

Copyright page (PDF)

pp. ii

Sponsors (PDF)

pp. iii

Table of contents (PDF)

pp. iv-vii

Message from the general chair (PDF)

Tor Aamodt , University of British Columbia, Canada
pp. viii

Message from the program chair (PDF)

Benjamin C. Lee , Duke University, USA
pp. ix-x

Bridging the energy-efficiency gap in a future of massive data (Abstract)

Fred Chong , University of California at Santa Barbara, USA
pp. 1

BarrierPoint: Sampled simulation of multi-threaded applications (Abstract)

Trevor E. Carlson , Ghent University, Belgium
Wim Heirman , Intel, ExaScience Lab, Belgium
Kenzo Van Craeynest , Ghent University, Belgium
Lieven Eeckhout , Ghent University, Belgium
pp. 2-12

Sources of error in full-system simulation (Abstract)

Anthony Gutierrez , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Joseph Pusdesris , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Ronald G. Dreslinski , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Trevor Mudge , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Chander Sudanthi , ARM Research - Austin, TX, USA
Christopher D. Emmons , ARM Research - Austin, TX, USA
Mitchell Hayenga , ARM Research - Austin, TX, USA
Nigel Paver , ARM Research - Austin, TX, USA
pp. 13-22

Exploiting spatial architectures for edit distance algorithms (Abstract)

Jesmin Jahan Tithi , Stony Brook University, USA
Neal C. Crago , VSSAD, Intel Corporation, USA
Joel S. Emer , VSSAD, Intel Corporation, USA
pp. 23-34

A Top-Down method for performance analysis and counters architecture (Abstract)

Ahmad Yasin , Intel Corporation, Architecture Group, USA
pp. 35-44

Moby: A mobile benchmark suite for architectural simulators (Abstract)

Yongbing Huang , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Zhongbin Zha , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Mingyu Chen , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Lixin Zhang , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 45-54

The design space of ultra-low energy asymmetric cryptography (Abstract)

Andrew D. Targhetta , Department of Electrical and Computer Engineering, Texas A&M University, USA
Donald E. Owen , Sandia National Laboratories, USA
Paul V. Gratz , Department of Electrical and Computer Engineering, Texas A&M University, USA
pp. 55-65

Optimized hardware for suboptimal software: The case for SIMD-aware benchmarks (Abstract)

Juan M. Cebrian , Dept. of Computer and Information Science (IDI), NTNU Trondheim, NO-7491, Norway
Magnus Jahre , Dept. of Computer and Information Science (IDI), NTNU Trondheim, NO-7491, Norway
Lasse Natvig , Dept. of Computer and Information Science (IDI), NTNU Trondheim, NO-7491, Norway
pp. 66-75

Applying the roofline model (Abstract)

Georg Ofenbeck , Department of Computer Science, ETH Zurich, Switzerland
Ruedi Steinmann , Department of Computer Science, ETH Zurich, Switzerland
Victoria Caparros , Department of Computer Science, ETH Zurich, Switzerland
Daniele G. Spampinato , Department of Computer Science, ETH Zurich, Switzerland
Markus Puschel , Department of Computer Science, ETH Zurich, Switzerland
pp. 76-85

Extending statistical cache models to support detailed pipeline simulators (Abstract)

Nikos Nikoleris , Uppsala University, Department of Information Technology, P.O. Box 337, SE-751 05, Sweden
David Eklov , Uppsala University, Department of Information Technology, P.O. Box 337, SE-751 05, Sweden
Erik Hagersten , Uppsala University, Department of Information Technology, P.O. Box 337, SE-751 05, Sweden
pp. 86-95

Modeling cache coherence misses on multicores (Abstract)

Xiaoyue Pan , Department of Information Technology, Uppsala University, Sweden
Bengt Jonsson , Department of Information Technology, Uppsala University, Sweden
pp. 96-105

Manifold: A parallel simulation framework for multicore systems (Abstract)

Jun Wang , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
Jesse Beu , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
Rishiraj Bheda , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
Tom Conte , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
Zhenjiang Dong , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
Chad Kersey , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
Mitchelle Rasquinha , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
George Riley , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
William Song , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
He Xiao , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
Peng Xu , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
Sudhakar Yalamanchili , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332-0250, USA
pp. 106-115

PriME: A parallel and distributed simulator for thousand-core chips (Abstract)

Yaosheng Fu , Princeton University, USA
David Wentzlaff , Princeton University, USA
pp. 116-125

A study of Thread Level Parallelism on mobile devices (Abstract)

Cao Gao , Advanced Computer Architecture Laboratory, University of Michigan, USA
Anthony Gutierrez , Advanced Computer Architecture Laboratory, University of Michigan, USA
Ronald G. Dreslinski , Advanced Computer Architecture Laboratory, University of Michigan, USA
Trevor Mudge , Advanced Computer Architecture Laboratory, University of Michigan, USA
Krisztian Flautner , ARM Ltd., UK
Geoffery Blake , ARM Ltd., UK
pp. 126-127

Transforming Java programs for concurrency using Double-Checked Locking pattern (Abstract)

Kazuaki Ishizaki , IBM Research - Tokyo, Japan
Shahrokh Daijavad , IBM Research - Almaden, USA
Toshio Nakatani , IBM Research - Tokyo, Japan
pp. 128-129

ParTejas: A parallel simulator for multicore processors (Abstract)

Geetika Malhotra , Computer Science Department, Indian Institute of Technology, Hauz Khas, New Delhi, India
Pooja Aggarwal , Computer Science Department, Indian Institute of Technology, Hauz Khas, New Delhi, India
Abhishek Sagar , Adobe Systems India, Adobe Towers, Noida, U.P, India
Smruti R. Sarangi , Adobe Systems India, Adobe Towers, Noida, U.P, India
pp. 130-131

Power modeling and other new features in the Graphite simulator (Abstract)

George Kurian , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA, USA
Sabrina M. Neuman , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA, USA
George Bezerra , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA, USA
Anthony Giovinazzo , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA, USA
Srinivas Devadas , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA, USA
Jason E. Miller , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA, USA
pp. 132-134

Accelerating network-on-chip simulation via sampling (Abstract)

Wenbo Dai , Department of Electrical and Computer Engineering, University of Toronto, Canada
Natalie Enright Jerger , Department of Electrical and Computer Engineering, University of Toronto, Canada
pp. 135-136

A case for resource efficient prefetching in multicores (Abstract)

Muneeb Khan , Department of Information Technology, Uppsala University, Sweden
Andreas Sandberg , Department of Information Technology, Uppsala University, Sweden
Erik Hagersten , Department of Information Technology, Uppsala University, Sweden
pp. 137-138

Evaluating trace aggregation for performance visualization of large distributed systems (Abstract)

Robin Lamarche-Perrin , Université Grenoble Alpes, Laboratoire d'Informatique de Grenoble, France
Lucas Mello Schnorr , CNRS, Laboratoire d'Informatique de Grenoble, France
Jean-Marc Vincent , Université Grenoble Alpes, Laboratoire d'Informatique de Grenoble, France
Yves Demazeau , CNRS, Laboratoire d'Informatique de Grenoble, France
pp. 139-140

Reverse engineering of cache replacement policies in Intel microprocessors and their evaluation (Abstract)

Andreas Abel , Department of Computer Science, Saarland University, Saarbrücken, Germany
Jan Reineke , Department of Computer Science, Saarland University, Saarbrücken, Germany
pp. 141-142

Energy Introspector: A parallel, composable framework for integrated power-reliability-thermal modeling for multicore architectures (Abstract)

William J. Song , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
Saibal Mukhopadhyay , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
Sudhakar Yalamanchili , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
pp. 143-144

Characterizing the latency hiding ability of GPUs (Abstract)

Shin-Ying Lee , Arizona State University, USA
Carole-Jean Wu , Arizona State University, USA
pp. 145-146

A software based profiling method for obtaining speedup stacks on commodity multi-cores (Abstract)

David Eklov , Uppsala University, Department of Information Technology, Sweden
Nikos Nikoleris , Uppsala University, Department of Information Technology, Sweden
Erik Hagersten , Uppsala University, Department of Information Technology, Sweden
pp. 148-157

MIAMI: A framework for application performance diagnosis (Abstract)

Gabriel Marin , Innovative Computing Laboratory, University of Tennessee, USA
Jack Dongarra , Innovative Computing Laboratory, University of Tennessee, USA
Dan Terpstra , Innovative Computing Laboratory, University of Tennessee, USA
pp. 158-168

Quality Time: A simple online technique for quantifying multicore execution efficiency (Abstract)

Anshuman Gupta , University of California, San Diego, USA
Jack Sampson , Pennsylvania State University, USA
Michael Bedford Taylor , University of California, San Diego, USA
pp. 169-179

Variability of data dependences and control flow (Abstract)

Tobias J.K. Edler von Koch , Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, 10 Crichton Street, EH8 9AB, U.K.
Bjorn Franke , Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh, 10 Crichton Street, EH8 9AB, U.K.
pp. 180-189

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads (Abstract)

Seth H Pugsley , University of Utah, USA
Jeffrey Jestes , University of Utah, USA
Huihui Zhang , University of Utah, USA
Rajeev Balasubramonian , University of Utah, USA
Vijayalakshmi Srinivasan , IBM T.J. Watson Research Center, USA
Alper Buyuktosunoglu , IBM T.J. Watson Research Center, USA
Al Davis , University of Utah, USA
Feifei Li , University of Utah, USA
pp. 190-200

Simulating DRAM controllers for future system architecture exploration (Abstract)

Andreas Hansson , Research & Development, ARM Ltd., Cambridge, United Kingdom
Neha Agarwal , Advanced Computer Architecture Lab, The University of Michigan, Ann Arbor, United States
Aasheesh Kolli , Advanced Computer Architecture Lab, The University of Michigan, Ann Arbor, United States
Thomas Wenisch , Advanced Computer Architecture Lab, The University of Michigan, Ann Arbor, United States
Aniruddha N. Udipi , Research & Development, ARM Inc., Austin, United States
pp. 201-210

Energy-efficient reconfigurable cache architectures for accelerator-enabled embedded systems (Abstract)

Amin Farmahini-Farahani , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, USA
Nam Sung Kim , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, USA
Katherine Morrow , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, USA
pp. 211-220

GPU-Qin: A methodology for evaluating the error resilience of GPGPU applications (Abstract)

Bo Fang , Department of Electrical and Computer Engineering, University of British Columbia, Canada
Karthik Pattabiraman , Department of Electrical and Computer Engineering, University of British Columbia, Canada
Matei Ripeanu , Department of Electrical and Computer Engineering, University of British Columbia, Canada
Sudhanva Gurumurthi , AMD Research, Advanced Micro Devices, Inc., USA
pp. 221-230

Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs (Abstract)

Chao Li , Department of Electrical and Computer Engineering, North Carolina State University, USA
Yi Yang , Department of Computing Systems Architecture, NEC Laboratories America, USA
Hongwen Dai , Department of Electrical and Computer Engineering, North Carolina State University, USA
Shengen Yan , Institute of Software, Chinese Academy of Sciences, North Carolina State University, USA
Frank Mueller , Department of Computer Science North Carolina State University, USA
Huiyang Zhou , Department of Electrical and Computer Engineering, North Carolina State University, USA
pp. 231-242

Author index (PDF)

pp. 243-244
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