The Community for Technology Leaders
2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (2006)
Austin, TX, USA
Mar. 19, 2006 to Mar. 21, 2006
ISBN: 1-4244-0186-0
TABLE OF CONTENTS

list-reviewer (PDF)

pp. vii
Papers

Copyright (PDF)

pp. ii

Quantitative system design (PDF)

M.K. Vernon , Wisconsin Univ., USA
pp. 130
Papers

Table of Contents (PDF)

pp. viii-x

Simulation sampling with live-points (Abstract)

B. Falsafi , Comput. Archit. Lab., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.C. Hoe , Comput. Archit. Lab., Carnegie Mellon Univ., Pittsburgh, PA, USA
T.F. Wenisch , Comput. Archit. Lab., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.E. Wunderlich , Comput. Archit. Lab., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 2-12

Accelerating architectural exploration using canonical instruction segments (Abstract)

R.F. Liu , Comput. Sci.&Artificial Intelligence Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA
K. Asanovic , Comput. Sci.&Artificial Intelligence Lab., Massachusetts Inst. of Technol., Cambridge, MA, USA
pp. 13-24

Branch trace compression for snapshot-based simulation (Abstract)

K. Asanovic , MIT Comput. Sci.&Artificial Intelligence Lab., Cambridge, MA, USA
K.C. Barr , MIT Comput. Sci.&Artificial Intelligence Lab., Cambridge, MA, USA
pp. 25-36

Critical path analysis of the TRIPS architecture (Abstract)

D. Burger , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
R.G. McDonald , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
null Xia Chen , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
S.W. Keckler , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
R. Nagarajan , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 37-47

Revisiting the performance impact of branch predictor latencies (Abstract)

G.H. Loh , Coll. of Comput., Georgia Inst. of Technol., USA
pp. 59-69

Evaluating the efficacy of statistical simulation for design space exploration (Abstract)

A. Joshi , Dept. of Electr.&Comput. Eng., Texas Univ., Austin, TX, USA
pp. 70-79

Comparing simulation techniques for microarchitecture-aware floorplanning (Abstract)

V. Nookala , Dept. of Electr.&Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
pp. 80-88

A statistical multiprocessor cache model (Abstract)

H. Zeffer , Dept. of Inf. Technol., Uppsala Univ., Sweden
E. Hagersten , Dept. of Inf. Technol., Uppsala Univ., Sweden
E. Berg , Dept. of Inf. Technol., Uppsala Univ., Sweden
pp. 89-99

Power efficient resource scaling in partitioned architectures through dynamic heterogeneity (Abstract)

N. Muralimanohar , Sch. of Comput., Utah Univ., USA
R. Balasubramonian , Sch. of Comput., Utah Univ., USA
K. Ramani , Sch. of Comput., Utah Univ., USA
pp. 100-111

Compiler-based adaptive fetch throttling for energy-efficiency (Abstract)

C.M. Krishna , Dept. of Electr.&Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren , Dept. of Electr.&Comput. Eng., Massachusetts Univ., Amherst, MA, USA
null Huaping Wang , Dept. of Electr.&Comput. Eng., Massachusetts Univ., Amherst, MA, USA
null Yao Guo , Dept. of Electr.&Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 112-119

Modeling TCAM power for next generation network devices (Abstract)

T. Sherwood , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
B. Agrawal , Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
pp. 120-129

Comparing multinomial and k-means clustering for SimPoint (Abstract)

G. Hamerly , Dept. of Comput. Sci., Baylor Univ., Waco, TX, USA
pp. 131-142

Considering all starting points for simultaneous multithreading simulation (Abstract)

B. Calder , California Univ., USA
M. Van Biesbrouckt , California Univ., USA
L. Eeckhout , California Univ., USA
pp. 143-153

Friendly fire: understanding the effects of multiprocessor prefetches (Abstract)

E.L. Hill , Dept. of Electr.&Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
M.H. Lipasti , Dept. of Electr.&Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
N.D.E. Jerger , Dept. of Electr.&Comput. Eng., Wisconsin-Madison Univ., Madison, WI, USA
pp. 177-188

Performance modeling and prediction for scientific Java applications (Abstract)

K. Kennedy , Dept. of Comput. Sci., Rice Univ., Houston, TX, USA
null Rui Zhang , Dept. of Comput. Sci., Rice Univ., Houston, TX, USA
Z. Budimlic , Dept. of Comput. Sci., Rice Univ., Houston, TX, USA
pp. 199-210

Assessing the impact of reactive workloads on the performance of Web applications (Abstract)

L. Silva , e-SPEED Lab., Fed. Univ. of Minas Gerais, Brazil
A. Pereira , e-SPEED Lab., Fed. Univ. of Minas Gerais, Brazil
W. Meira , e-SPEED Lab., Fed. Univ. of Minas Gerais, Brazil
W. Santos , e-SPEED Lab., Fed. Univ. of Minas Gerais, Brazil
pp. 211-220

Workload sanitation for performance evaluation (Abstract)

D.G. Feitelson , Sch. of Comput. Sci.&Eng., Hebrew Univ., Israel
D. Tsafrir , Sch. of Comput. Sci.&Eng., Hebrew Univ., Israel
pp. 221-230

ATTILA: a cycle-level execution-driven simulator for modern GPU architectures (Abstract)

V.M. del Barrio , Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Spain
C. Gonzalez , Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Spain
J. Roca , Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Spain
A. Fernandez , Dept. of Comput. Archit., Univ. Politecnica de Catalunya, Spain
pp. 231-241

Acquisition and evaluation of long DDR2-SDRAM access sequences (Abstract)

S. Kalms , Infineon Technol. AG, Munich, Germany
S. Albert , Infineon Technol. AG, Munich, Germany
A. Schramm , Infineon Technol. AG, Munich, Germany
C. Weiss , Infineon Technol. AG, Munich, Germany
pp. 242-250

Aestimo: a feedback-directed optimization evaluation tool (Abstract)

J.N. Amaral , Dept. of Comput. Sci., Alberta Univ., Edmonton, Alta., Canada
P. Berube , Dept. of Comput. Sci., Alberta Univ., Edmonton, Alta., Canada
pp. 251-260
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