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2000 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS (Cat. No.00EX422) (2000)
Austin, TX, USA
Apr. 24, 2000 to Apr. 25, 2000
ISBN: 0-7803-6418-X
TABLE OF CONTENTS
Ispass

Performance analysis through synthetic trace generation (Abstract)

L. Eeckhout , Dept. of Electron. & Inf. Syst., Ghent Univ., Belgium
pp. 1-6

Accurate simulation and evaluation of code reordering (Abstract)

J. Kalamatianos , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 13-20

Quantifying instruction-level parallelism limits on an EPIC architecture (Abstract)

Hsien-Hsin Lee , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 21-27

Performance evaluation of real-time scheduling on a multicomputer architecture (Abstract)

L.F. Friedrich , Dept. de Inf. e de Estatistica, Univ. Federal de Santa Catarina, Florianopolis, Brazil
pp. 28-33

Performance evaluation of middleware bridging technologies (Abstract)

R. Fatoohi , Comput. Eng., San Jose State Univ., CA, USA
pp. 34-39

DB2 for OS/390 V5 vs. V6 outer join performance (Abstract)

M. Weihrauch , Santa Teresa Lab., IBM, San Jose, CA, USA
pp. 46-51

Checking order-insensitivity using ternary simulation in synchronous programs (Abstract)

M. Yeddes , INPG, Univ. Joseph Fourier, St. Martin d'Heres, France
pp. 52-57

Do generational schemes improve the garbage collection efficiency? (Abstract)

W. Srisa-an , Dept. of Comput. Sci., Illinois Inst. of Technol., Chicago, IL, USA
pp. 58-63

A quantitative simulator for dynamic memory managers (Abstract)

J.M. Chang , Dept. of Comput. Sci., Illinois Inst. of Technol., Chicago, IL, USA
pp. 64-69

Real-time image on QoS Web (Abstract)

Hong Liu , Dept. of Electr. & Comput. Eng., Massachusetts Univ., Dartmouth, MA, USA
pp. 70-75

Issues in the design of store buffers in dynamically scheduled processors (Abstract)

R. Bhargava , Lab. for Comput. Archit., Texas Univ., Austin, TX, USA
pp. 76-87

Performance tradeoffs in sequencer design on a new G4 PowerPC/sup TM/ microprocessor (Abstract)

L.K. John , Somerset Design Center, Motorola Inc., Austin, TX, USA
pp. 88-94

Instruction overhead and data locality effects in superscalar processors (Abstract)

M. Annavaram , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 95-100

Modeling load address behaviour through recurrences (Abstract)

L. Ramos , Dept. Inf. e Ingenieria de Sistemas, Zaragoza Univ., Spain
pp. 101-108

Invocation profile characterization of Java applications (Abstract)

A. Barisone , Dept. of Electron. & Biophys. Eng., Genoa Univ., Italy
pp. 116-122

Some observations based on simple models of MP scaling (Abstract)

E. Kronstadt , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 123-128

Performance scalability in multiprocessor systems with resource contention (Abstract)

S. Majumdar , Dept. of Syst. & Comput. Eng., Carleton Univ., Ottawa, Ont., Canada
pp. 129-138

An efficient solver for Cache Miss Equations (Abstract)

N. Bermudo , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 139-145

An analytical model for loop tiling and its solution (Abstract)

V. Sarkar , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 146-153

CommBench-a telecommunications benchmark for network processors (Abstract)

T. Wolf , Dept. of Comput. Sci. & Electr. Eng., Washington Univ., St. Louis, MO, USA
pp. 154-162

A new approach in the analysis and modeling of disk access patterns (Abstract)

M.E. Gomez , Dept. de Sistemas Inf. y Comput., Univ. Politecnica de Valencia, Spain
pp. 172-177

Mobile functionality in a pervasive world (Abstract)

J. Jagiello , Dept. of Defence, Defence Sci. & Technol. Organ., Canberra, ACT, Australia
pp. 178-183

Design alternatives for scalable Web server accelerators (Abstract)

Junehwa Song , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 184-192

Web latency reduction via client-side prefetching (Abstract)

A.N. Eden , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 193-200

A server performance model for static Web workloads (Abstract)

K. Kant , Server Archit. Lab., Intel Corp., USA
pp. 201-206

Author Index (Abstract)

pp. 207
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