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International Symposium on Parallel and Distributed Processing with Applications (2008)
Dec. 10, 2008 to Dec. 12, 2008
ISBN: 978-0-7695-3471-8
pp: 335-342
Vector supercomputers have been encountering the memory wall problem and their memory bandwidth per flop/s rate has decreased. To cover the insufficient memory bandwidth per flop/s rate, an on-chip vector cache has been proposed for the vector processors. Although vector caching is effective to increase the sustained performance to a certain degree, it still needs software and hardware supporting mechanisms to extract its potential. To this end, we propose miss status handling registers (MSHR) and a prefetch mechanism. This paper evaluates the performance of the vector cache with the MSHR and the prefetch mechanism on the vector supercomputer across three leading scientific applications. The MSHR is an effective mechanism for handling subsequent vector loads of the same data, which frequently appear in different schemes. The experimental results indicate that the MSHR can improve the computational performance of scientific applications by 1.45
Vector architecture, Vector cache, MSHR, Prefetch, Performance characterization, Memory system

H. Takizawa et al., "Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture," 2008 IEEE International Symposium on Parallel and Distributed Processing with Applications(ISPA), Sydney, NSW, 2008, pp. 335-342.
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