2012 IEEE 42nd International Symposium on Multiple-Valued Logic (2012)
Victoria, British Columbia Canada
May 14, 2012 to May 16, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2012.72
In this paper, a synthesis flow for sequential reversible circuits is proposed. In particular, a methodology is introduced which transforms a finite state machine into a Boolean function representing the sequential behavior. Having that, any combinational synthesis approach can be exploited in order to perform the actual synthesis. Heuristics ensure that encodings for the states are applied which keep the costs of the resulting circuits low. Experiments show the applicability of the approach.
C. Otterstedt, R. Wille, R. Drechsler and M. Soeken, "A Synthesis Flow for Sequential Reversible Circuits," 2012 IEEE 42nd International Symposium on Multiple-Valued Logic(ISMVL), Victoria, British Columbia Canada, 2012, pp. 299-304.