2012 IEEE 42nd International Symposium on Multiple-Valued Logic (2012)
Victoria, British Columbia Canada
May 14, 2012 to May 16, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2012.20
Cyclic Redundancy Check codes (CRC) are widely used in data communication and storage devices for detecting burst errors. In applications requiring high-speed data transmission, multiple bits of an CRC are computed in parallel. Traditional methods for constructing an Linear Feedback Shift Register (LFSR) generating $k$ bits of an CRC in parallel are based on computing $k$th power of the connection matrix of the LFSR. We propose an alternative method which is based on computing $k$th power of the transition relation of the LFSR. We use Binary Decision Diagrams (BDDs) for representing the transition relation and we keep the transition relation partitioned. This allows us to bound the size of BDDs by $O(n^2)$, where $n$ is the size of the LFSR. Our experimental results show that the presented algorithm asymptotically improves the complexity of previous approaches.
parallel CRC, LFSR, BDD
E. Dubrova and S. S. Mansouri, "A BDD-Based Approach to Constructing LFSRs for Parallel CRC Encoding," 2012 IEEE 42nd International Symposium on Multiple-Valued Logic(ISMVL), Victoria, British Columbia Canada, 2012, pp. 128-133.