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2013 IEEE 43rd International Symposium on Multiple-Valued Logic (2011)
Tuusula, Finland
May 23, 2011 to May 25, 2011
ISSN: 0195-623X
ISBN: 978-0-7695-4405-2
pp: 170-175
Driven by its promising applications, reversible logic received significant attention. As a result, an impressive progress has been made in the development of synthesis approaches, implementation of sequential elements, and hardware description languages. In this paper, these recent achievements are employed in order to design a RISC CPU in reversible logic that can execute software programs written in an assembler language. The respective combinational and sequential components are designed using state-of-the-art design techniques.
reversible circuits, synthesis, design, cpu, hardware describing language, SyReC
Eleonora Schönborn, Mathias Soeken, Robert Wille, Rolf Drechsler, Daniel Große, "Designing a RISC CPU in Reversible Logic", 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, vol. 00, no. , pp. 170-175, 2011, doi:10.1109/ISMVL.2011.39
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