The Community for Technology Leaders
2011 41st IEEE International Symposium on Multiple-Valued Logic (2011)
Tuusula, Finland
May 23, 2011 to May 25, 2011
ISSN: 0195-623X
ISBN: 978-0-7695-4405-2
pp: 170-175
ABSTRACT
Driven by its promising applications, reversible logic received significant attention. As a result, an impressive progress has been made in the development of synthesis approaches, implementation of sequential elements, and hardware description languages. In this paper, these recent achievements are employed in order to design a RISC CPU in reversible logic that can execute software programs written in an assembler language. The respective combinational and sequential components are designed using state-of-the-art design techniques.
INDEX TERMS
reversible circuits, synthesis, design, cpu, hardware describing language, SyReC
CITATION

E. Schönborn, M. Soeken, R. Wille, R. Drechsler and D. Große, "Designing a RISC CPU in Reversible Logic," 2011 41st IEEE International Symposium on Multiple-Valued Logic(ISMVL), Tuusula, Finland, 2011, pp. 170-175.
doi:10.1109/ISMVL.2011.39
99 ms
(Ver 3.3 (11022016))