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2010 40th IEEE International Symposium on Multiple-Valued Logic (2010)
Barcelona, Spain
May 26, 2010 to May 28, 2010
ISSN: 0195-623X
ISBN: 978-0-7695-4024-5
pp: 128-133
Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is based on Field Effect Transistors (FETs) that have different voltage threshold levels. The resulting logic cell library is sufficient to implement all possible quaternary switching functions. The logic circuits operate in voltage mode where different ranges of voltages encode the logic levels. Voltage mode circuitry is used to minimize overall power dissipation characteristics. Analysis of the resulting multiplication circuits indicates that power dissipation characteristics are advantageous when compared to equivalent word-sized binary voltage mode configurations with no decrease in performance.
quaternary logic, arithmetic logic circuits

S. R. Datla and M. A. Thornton, "Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits," 2010 40th IEEE International Symposium on Multiple-Valued Logic(ISMVL), Barcelona, Spain, 2010, pp. 128-133.
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