2013 IEEE 43rd International Symposium on Multiple-Valued Logic (2009)
Naha, Okinawaw, Japan
May 21, 2009 to May 23, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2009.45
The synthesis and simplification of digital circuits are performed in the well known two level logic switching algebra. By increasing the representation domain to B levels it is possible to design Multiple-Valued Logic (MV Logic)digital circuits. This work proposes an algebra based on a universal set of gates which carry out operators to allow synthesis and simplification of MV Logic digital circuits. This paper addresses: the generated algebra; the algebraic form of the function to be synthesized based on the canonical form of the Sum Of Extended Product terms; the duality; and circuit simplification procedures. Combinatorial and sequential circuits are synthesized to demonstrate the correctness of the algebra. The proposed algebra allows designing any MV Logic digital circuit taking advantage of the knowledge coming from the binary circuits by extending it to the MV Logic digital circuit synthesis.
MVL Algebra, MVL, Synthesis, Digital Circuits
Milton E.R. Romero, Ricardo R. Santos, Evandro M. Martins, "Multiple Valued Logic Algebra for the Synthesis of Digital Circuits", 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, vol. 00, no. , pp. 262-267, 2009, doi:10.1109/ISMVL.2009.45