The Community for Technology Leaders
2013 IEEE 43rd International Symposium on Multiple-Valued Logic (2007)
Oslo, Norway
May 13, 2007 to May 16, 2007
ISSN: 0195-623X
ISBN: 0-7695-2831-7
TABLE OF CONTENTS
Introduction

Reviewers (PDF)

pp. x
Keynote
Invited Paper
Session 1A: Theory 1

Automated Reasoning in Some Local Extensions of Ordered Structures (Abstract)

Carsten Ihlemann , Max-Planck-Institut fur Informatik, Germany
Viorica Sofronie-Stokkermans , Max-Planck-Institut fur Informatik, Germany
pp. 1

Model-Characterizing Formulas and Normal Forms in Godel Logics (Abstract)

Heng Zhang , Guizhou University, Guizhou Normal University, China
Mingyi Zhang , Guizhou Normal University, Guizhou Academy of Sciences, China
pp. 3
Session 1B: Logic Functions

Spectral Analysis of Special Properties of Ternary Functions (Abstract)

Milena Stankovic , University of Nis, Serbia
Suzana Stojkovic , University of Nis, Serbia
Claudio Moraga , European Centre for Soft Computing, Spain
pp. 4

Representations of Elementary Functions Using Edge-Valued MDDs (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Japan
Shinobu Nagayama , Hiroshima City University, Japan
pp. 5

Experimental Studies on SAT-Based ATPG for Gate Delay Faults (Abstract)

Rolf Drechsler , University of Bremen, Germany
Jurgen Schloffel , NXP Semiconductors GmbH, Germany
Friedrich Hapke , NXP Semiconductors GmbH, Germany
Gorschwin Fey , University of Bremen, Germany
Andreas Glowatz , NXP Semiconductors GmbH, Germany
Daniel Tille , University of Bremen, Germany
Stephan Eggersgl? , University of Bremen, Germany
pp. 6
Session 2A: Theory 2 (Clones)

Polynomials as Generators of Minimal Clones (Abstract)

Hajime Machida , Hitotsubashi University, Japan
Michael Pinsker , TU Wien, Austria
pp. 7

Restriction-Closed Hyperclones (Abstract)

B.A. Romov , Bayard Rustin Educational Complex, USA
pp. 8

Monoidal Intervals of Partial Clones (Abstract)

H. Machida , Hitotsubashi University, Japan
I.G. Rosenberg , Universite de Montreal, Canada
L. Haddad , College militaire royal du Canada, Canada
pp. 9
Session 2B: Quantium Computing 1

Variable Reordering and Sifting for QMDD (Abstract)

David Y. Feinstein , Southern Methodist University, USA
D. Michael Miller , University of Victoria, Canada
Mitchell A. Thornton , Southern Methodist University, USA
pp. 10

GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits (Abstract)

Mozammel H.A. Khan , East West University, Bangladesh
Marek A. Perkowski , Portland State University, USA
pp. 11
Session 3A: Theory 3

The Genetic Code as a Multiple-Valued Function and Its Implementation Using Multilayer Neural Network Based on Multi-Valued Neurons (Abstract)

Igor Aizenberg , Texas A&M University-Texarkana, USA
Claudio Moraga , European Centre for Soft Computing, Spain; University of Dortmund, Germany
pp. 13

Non-deterministic Multi-valued Matrices for First-Order Logics of Formal Inconsistency (Abstract)

Arnon Avron , Tel-Aviv University, Israel
Anna Zamansky , Tel-Aviv University, Israel
pp. 14

New Fastest Linearly Independent Transforms over GF(3) (Abstract)

Tadeusz Luba , Warsaw University of Technology, Poland
Cicilia C. Lozano , Nanyang Technological University, Singapore
Bogdan J. Falkowski , Nanyang Technological University, Singapore
pp. 15

Inversion/Division in Galois Field Using Multiple-Valued Logic (Abstract)

Nabil Abu-Khader , Wayne State University, USA
Pepe Siy , Wayne State University, USA
pp. 16
Session 3B: Quantium Computing 2

Boolean Functions of Low Polynomial Degree for Quantum Query Complexity Theory (Abstract)

Liva Garkaje , Agenskalna Valsts gimnazija, Latvia
Rusins Freivalds , University of Latvia, Latvia
pp. 17

Quantum Robots for Teenagers (Abstract)

Marek Perkowski , Portland State University, USA
Yale Fan , The Catlin Gabel School, USA
Arushi Raghuvanshi , Valley Catholic Middle School, USA
Michal Woyke , Gymnasium Number 20, Poland
pp. 18

Quantum Mechanical Model of Emotional Robot Behaviors (Abstract)

Marek Perkowski , Portland State University, USA
Martin Lukac , Portland State University, USA
pp. 19

Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates (Abstract)

Asif I. Khan , Bangladesh University of Engineering and Technology, Bangladesh
Samira M. Khan , Bangladesh University of Engineering and Technology, Bangladesh
Mozammel H.A. Khan , East West University, Bangladesh
Masud Hasan , Bangladesh University of Engineering and Technology, Bangladesh
Nadia Nusrat , Bangladesh University of Engineering and Technology, Bangladesh
pp. 20
Session 4A: Theory 4

2-SAT Problems in Some Multi-Valued Logics Based on Finite Lattices (Abstract)

Witold Charatonik , University of Wroclaw, Poland
Michal Wrona , University of Wroclaw, Poland
pp. 21

A Complete Resolution Calculus for Signed Max-SAT (Abstract)

Carlos Ansotegui , DIEI UdL, Spain
Jordi Levy , IIIA, CSIC, Spain
Maria L. Bonet , LSI, UPC, Spain
Felip Manya , DIEI UdL, Spain
pp. 22

Efficient Algorithm for Calculation of Quaternardy Fixed Polarity Arithmetic Expansions (Abstract)

Tadeusz Luba , Warsaw University of Technology, Poland
Cicilia C. Lozano , Nanyang Technological University, Singapore
Bogdan J. Falkowski , Nanyang Technological University, Singapore
pp. 23
Session 4B: Circuit Design 1

Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices (Abstract)

Sarma B.K. Vrudhula , Arizona State University, USA
Krzysztof S. Berezowski , Wroclaw University of Technology, Poland
pp. 24
Session 5A: Theory 5

The Rough Powerset Monad (Abstract)

M.A. Galan , University of Malaga, Spain
P. Eklund , Umea University, Sweden
pp. 27

Exploiting Homogeneous Dual Polarity Routes in Implementation of Algorithms for Optimization of Galois Field Expressions for Ternary Functions (Abstract)

Dragan Jankovic , University of Nis, Serbia
Radomir S. Stankovic , University of Nis, Serbia
Claudio Moraga , University of Dortmund, Germany; European Centre for Soft Computing, Spain
pp. 28

Automated Reasoning Algorithm for Linguistic Valued Lukasiewicz Propositional Logic (Abstract)

Luis Martinez Lopez , University of Jaen, Spain
Yang Xu , Southwest Jiaotong University, China
Jun Liu , University of Ulster, UK
Zhirui Lu , University of Ulster, UK
pp. 29
Session 5B: Circuit Design 2

Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams (Abstract)

Naofumi Homma , Tohoku University, Japan
Tatsuo Higuchi , Tohoku Institute of Technology, Japan
Katsuhiko Degawa , Tohoku University, Japan
Takafumi Aoki , Tohoku University, Japan
pp. 31

On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters-- (Abstract)

Yukihiro Iguchi , Meiji University, Japan
Tsutomu Sasao , Kyushu Institute of Technology, Japan
Munehiro Matsuura , Kyushu Institute of Technology, Japan
pp. 32
Session 6A: Theory 6

On the Axiomatization of Generalized Entropic Metrics (Abstract)

Dan A. Simovici , Univ. of Massachusetts Boston, USA
pp. 33

Characterization of Partial Sheffer Functions in 3-Valued Logic (Abstract)

Dietlinde Lau , Universitat Rostock, Germany
Lucien Haddad , College militaire royal du Canada, Canada
pp. 34

Power Indexes in Voting Systems and Multiple-Valued Logic (Abstract)

Yoshinori Yamamoto , Takasaki City Univ. of Economics, Japan
pp. 35
Session 6B: Circuit 3

A Ternary Analog-to-Digital Converter System (Abstract)

Munehiko Nagatani , Sophia University, Japan
Tomoki Tanoue , Sophia University, Japan
Takao Waho , Sophia University, Japan
pp. 36

Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices (Abstract)

Rene Jensen , University of Oslo, Norway
Yngvar Berg , University of Oslo, Norway
pp. 37

Fault Tolerant CMOS Logic Using Ternary Gates (Abstract)

Yngvar Berg , University of Oslo, Norway
Johannes Lomsdalen , University of Oslo, Norway
Snorre Aunet , University of Oslo, Norway
Rene Jensen , University of Oslo, Norway
Henning Gundersen , University of Oslo, Norway
pp. 38
Session 7A: Theory 7

Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation (Abstract)

Tasuku Ito , Tohoku University, Japan
Michitaka Kameyama , Tohoku University, Japan
pp. 39

Linearization of Ternary Decision Diagrams by Using the Polynomial Chrestenson Spectrum (Abstract)

Milena Stankovic , University of Nis, Serbia
Claudio Moraga , European Centre of Soft Computing, Spain
Suzana Stojkovic , University of Nis, Serbia
pp. 41
Session 7B: Circuit Design 4

Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC (Abstract)

Andre Sulflow , University of Bremen, Germany
Rolf Drechsler , University of Bremen, Germany
pp. 42

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor (Abstract)

Kazutami Arimoto , Renesas Technology Corporation, Japan
Akira Mochizuki , Tohoku University, Japan
Hirokatsu Shirahama , Tohoku University, Japan
Masami Nakajima , Renesas Technology Corporation, Japan
Takahiro Hanyu , Tohoku University, Japan
pp. 43
Session 8A: Theory 8

Classifications and Enumeration of Bases in P_{3}(2) (Abstract)

Masahiro Miyakawa , Tsukuba University of Technology, Japan
Dietlinde Lau , University of Rostock, Germany
pp. 45

Simulation of Gate Circuits with Feedback in Multi-Valued Algebras (Abstract)

Yuli Ye , University of Toronto, Canada
Janusz Brzozowski , University of Waterloo, Canada
pp. 46

Properties and Fast Algorithms for Ternary Walsh Transform (Abstract)

Bogdan J. Falkowski , Nanyang Technological University, Singapore
Shixing Yan , HP Labs China
pp. 47
Session 8B: Circuit Design 5

Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions (Abstract)

M. Yamamoto , Hokkaido University, Japan
T. Uemura , Hokkaido University, Japan
T. Marukame , Hokkaido University, Japan
K.-i. Matsuda , Hokkaido University, Japan
pp. 49

Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL (Abstract)

Rolf Drechsler , University of Bremen, Germany
Mahsan Amoui , Southern Methodist University, USA
Mitchell A. Thornton , Southern Methodist University, USA
Daniel Gro?e , University of Bremen, Germany
pp. 50

Limits to a Correct Evaluation in RTD-Based Quaternary Inverters (Abstract)

Maria J. Avedillo , IMSE-CNM-CSIC, Spain
Juan Nunez , IMSE-CNM-CSIC, Spain
Jose M. Quintana , IMSE-CNM-CSIC, Spain
pp. 51

Evaluation and Comparison of Threshold Logic Gates (Abstract)

Elena Dubrova , Royal Institute of Technology (KTH), Sweden
Vasilios Lirigis , Royal Institute of Technology (KTH), Sweden
pp. 52
Session 9A: Circuit Design 6

Towards First-Order Symbolic Trajectory Evaluation (Abstract)

Sa'ed Abed , Concordia University, Canada
Otmane Ait-Mohamed , Concordia University, Canada
Donglin Li , Concordia University, Canada
pp. 53

Survey of Stochastic Computation on Factor Graphs (Abstract)

Shie Mannor , McGill University, Canada
Warren J. Gross , McGill University, Canada
Saeed Sharifi Tehrani , McGill University, Canada
pp. 54
Session 9B: Circuit Design 7

Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design (Abstract)

Ricardo Cunha , Universidade Federal do Rio Grande do Sul, Brazil
Henri Boudinov , Universidade Federal do Rio Grande do Sul, Brazil
Luigi Carro , Universidade Federal do Rio Grande do Sul, Brazil
pp. 56
Author Index

Author Index (PDF)

pp. 59
111 ms
(Ver 3.1 (10032016))