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2013 IEEE 43rd International Symposium on Multiple-Valued Logic (2006)
Singapore
May 17, 2006 to May 20, 2006
ISSN: 0195-623X
ISBN: 0-7695-2532-6
TABLE OF CONTENTS
Introduction
Introduction
Session 1: Invited Address

Design Methods for Multiple-Valued Input Address Generators (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Japan
pp. 1
Session 2: Circuits I

Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic (Abstract)

Takafumi Aoki , Tohoku University, Sendai, Japan
Naofumi Homma , Tohoku University, Sendai, Japan
Tatsuo Higuchi , Tohoku Institute of Technology, Japan
pp. 2

On Designs of Radix Converters Using Arithmetic Decompositions (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Iizuka , Japan
Munehiro Matsuura , Kyushu Institute of Technology, Iizuka , Japan
Yukihiro Iguchi , Meiji University, Kawasaki 214-8571, Japan
pp. 3

Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture (Abstract)

Haque Mohammad Munirul , Tohoku University, Japan
Michitaka Kameyama , Tohoku University, Japan
Tomoaki Hasegawa , Tohoku University, Japan
pp. 6
Session 3: Algebra and Logic

On the Ranges of Algebraic Functions in Lattices - A Preliminary Report (Abstract)

Dan A. Simovici , Univ. of Massachusetts, Boston
Sergiu Rudeanu , University of Bucharest, Romania
pp. 7

Upper and Lower Bounds on the Number of Disjunctive Forms (Abstract)

Masahiro MIYAKAWA , Tsukuba University of Technology, Japan
Hisayuki TATSUMI , Tsukuba University of Technology, Japan
Masao MUKAIDONO , Meiji University, Japan
pp. 8

Completeness of a Hypersequent Calculus for Some First-order Godel Logics with Delta (Abstract)

Matthias Baaz , Technische Universitat Wien, Vienna, Austria
Norbert Preining , Universit`a di Siena, Italy
Richard Zach , University of Calgary
pp. 9
Session 4: Circuits II

Implementation of Multiple-Valued CAM Functions by LUT Cascades (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology, Japan
Jon T. Butler , Naval Postgraduate School, Monterey, CA.
pp. 11

The new architecture of radix-4 Chinese abacus adder (Abstract)

Chuen-Ching Wang , National Changhua University of Education, Changhua, Taiwan
Jin-Jia Chen , National Changhua University of Education, Changhua, Taiwan
Chien-Hung Lin , National Changhua University of Education, Changhua, Taiwan
Shu-Chung Yi , National Changhua University of Education, Changhua, Taiwan
Kun-Tse Lee , National Changhua University of Education, Changhua, Taiwan
Chin-Fa Hsieh , China Institute of Technology, Taipei, Taiwan
Chih-Yung Lu , China Institute of Technology, Taipei, Taiwan
pp. 12

Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits (Abstract)

Takahiro Hanyu , Tohoku University, Japan
Akira Mochizuki , Tohoku University, Japan
Takeshi Kitamura , Tohoku University, Japan
Hirokatsu Shirahama , Tohoku University, Japan
pp. 14
Session 5: Invited Address

Signal Processing Algorithms and Multiple-Valued Logic Design Methods (Abstract)

Radomir S. Stankovic , Dept. of Computer Science, Faculty of Electronics, 18000 Nis, Serbia
Jaakko Astola , Tampere University of Technology, Finland
pp. 16
Session 6: Circuits III

Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals (Abstract)

Yoshihiro NAKATANI , Graduate School of Information Sciences, Tohoku Univers, Japan
Masanori HARIYAMA , Graduate School of Information Sciences, Tohoku Univers, Japan
Michitaka KAMEYAMA , Graduate School of Information Sciences, Tohoku Univers, Japan
pp. 17

A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices (Abstract)

Henning Gundersen , University of Oslo, Norway
Yngvar Berg , University of Oslo, Norway
pp. 18

A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors (Abstract)

Hiroshi Inokawa , NTT Corporation, Japan
Takafumi Aoki , Tohoku University, Sendai 980-8579, Japan
Yasuo Takahashi , Graduate School of Information Science and Technology, Hokkaido University, Japan
Katsuhiko Degawa , Tohoku University, Sendai 980-8579, Japan
Katsuhiko Nishiguchi , NTT Corporation, Japan
Tatsuo Higuchi , Tohoku Institute of Technology, Japan
pp. 19
Session 7: Algebra and Clones

Commuting Hyperoperations (Abstract)

Gradimir Vojvodic , University of Novi Sad, Serbia and Montenegro
Jovanka Pantovic , University of Novi Sad, Serbia and Montenegro
pp. 21

Theoretical Basis of Commutation Theory for Partial Clones (Abstract)

Lucien Haddad , Lucien Haddad
Hajime Machida , Hajime Machida
Ivo G. Rosenberg , Ivo G. Rosenberg
pp. 22

Associativity Test in Hypergroupoids (Abstract)

Ivo G. Rosenberg , Universite de Montreal, Canada
Hisayuki Tatsumi , Tsukuba Unversity of Technology, Japan
Masahiro Miyakawa , Tsukuba University of Technology, Japan
pp. 23

Some Observations on Minimal Clones (Abstract)

Hajime Machida , Hajime Machida
Michael Pinsker , Michael Pinsker
pp. 24
Session 8: Systems and Satisfiability

Efficiency of Multi-Valued Encoding in SAT-based ATPG (Abstract)

Junhao Shi , University of Bremen, Germany
Goerschwin Fey , University of Bremen, Germany
Rolf Drechsler , University of Bremen, Germany
pp. 25

Towards Solving Many-Valued MaxSAT (Abstract)

Chu-Min Li , Universite de Picardie, France
Felip Manya , IIIA-CSIC, Spain
Jordi Planes , Universitat de Lleida, Spain
Xavier Domingo , GPS MicroSAT, Spain
Josep Argelich , Universitat de Lleida, Spain
pp. 26

Random Multiple-Valued Networks: Theory and Applications (Abstract)

Elena Dubrova , Royal Institute of Technology, IMIT/KTH, Sweden
pp. 27
Session 9: Decision Diagrams and Decision Trees

Representations of Elementary Functions Using Binary Moment Diagrams (Abstract)

Shinobu Nagayama , Hiroshima City University, Japan
Tsutomu Sasao , Kyushu Institute of Technology, Japan
pp. 28

Embedding and Assembling Techniques for Spatial Computing Structure Design using Decision Trees and Diagrams (Abstract)

O. R. Boulanov , University of Calgary, Canada
V. P. Shmerko , University of Calgary, Canada
S. N. Yanushkevich , University of Calgary, Canada
pp. 29

QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits (Abstract)

Mitchell A. Thornton , Southern Methodist University, Dallas, TX, USA
D. Michael Miller , University of Victoria, Victoria, BC, Canada
pp. 30

Arithmetic-Haar Spectral Transform Decision Diagrams (Abstract)

Bogdan J. Falkowski , Nanyang Technological University, Singapore
Shixing Yan , Nanyang Technological, Singapore
pp. 31
Session 10: Quantum Logic and Spectral Techniques

Multi-Valued Quantum Logic (Abstract)

Michael Katz , Haifa University, Mount Carmel, Haifa, Israel
pp. 32

A Quantum CAD Accelerator Based on Grover?s Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form (Abstract)

Mitch Thornton , Southern Methodist University, Dallas, TX
Marek Perkowski , Portland State University, Portland, OR
Lun Li , Southern Methodist University, Dallas, TX
pp. 33

Generation and Relation of Quaternary and Binary Linearly Independent Transforms (Abstract)

Bogdan J. Falkowski , Nanyang Technological University, Singapore
Cheng Fu , Nanyang Technological University, Singapore
pp. 34

Properties of matrix-valued spectral coefficients obtained with the Fourier Transform on a non-Abelian group (Abstract)

Radomir Stankovic , Dept. Computer Science Faculty of Electronics, Serbia
Jaakko Astola , Tampere University of Technology, Finland
Claudio Moraga , European Center of Soft Computing de Barredo Building of Sc. and Tech., Spain
pp. 35
Author Index

Author Index (PDF)

pp. 36
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