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2013 IEEE 43rd International Symposium on Multiple-Valued Logic (2000)
Portland, Oregon
May 23, 2000 to May 25, 2000
ISSN: 0195-623X
ISBN: 0-7695-0692-5

Reviewers (PDF)

pp. xiv
Session 1: Invited Address
Session 2a: Neural and Threshold Nets

Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors (Abstract)

Koichi Tanno , Miyazaki University
Okihiko Ishizuka , Miyazaki University
Motoi Inaba , Miyazaki University
Jing Shen , Miyazaki University
pp. 15

Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions (Abstract)

Jing Shen , Miyazaki University
Makoto Syuto , Miyazaki University
Okihiko Ishizuka , Miyazaki University
Koichi Tanno , Miyazaki University
pp. 27

The Computing Capacity of Three-Input Multiple-Valued One-Threshold Perceptrons (Abstract)

Alioune Ngom , Lakehead University
Ivan Stojmenovic , University of Ottawa
Ratko To?ic , University of Novi Sad
pp. 33
Session 2b: Spectral Methods

MDD-Based Synthesis of Multi-Valued Logic Networks (Abstract)

Rolf Drechsler , Albert-Ludwigs-University
David Wessels , University of Arkansas
Mitch Thornton , Mississippi State University
pp. 41

Fast Transforms for Multiple-Valued Input Binary Output PLI Logic (Abstract)

Susanto Rahardja , Nanyang Technological University
Bogdan J. Falkowski , Nanyang Technological University
pp. 47

Computation of Spectral Information from Logic Netlists (Abstract)

Mitch Thornton , Mississippi State University
Rolf Drechsler , Albert-Ludwigs-University
pp. 53

Fault Analysis of the Multiple Valued Logic Using Spectral Method (Abstract)

Jong O Kim , Dongyang Technical College
Heung Soo Kim , Inha University
Young Gun Kim , Ansan College
Parag Lala , University of Arkansas
pp. 59
Session 3: Invited Address
Session 4a: Decomposition and Data Mining

Data Mining of Weak Functional Decompositions (Abstract)

Dan A. Simovici , University of Massachusetts at Boston
Szymon Jaroszewicz , University of Massachusetts at Boston
pp. 77

Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures (Abstract)

Artur Chojnacki , Eindhoven University of Technology
Lech Józwiack , Eindhoven University of Technology
pp. 83
Session 4b: Algebra I

Some Properties of Discrete Interval Truth Valued Logic (Abstract)

Kyoichi Nakashima , Toyama Prefectural University
Noboru Takagi , Toyama Prefectural University
pp. 101

On Urquhart's C Logic (Abstract)

Agata Ciabattoni , Universit? Milano
pp. 113
Session 5a: Fuzzy Logic

A New Class of Fuzzy Modifiers (Abstract)

Martine de Cock , Ghent University
Etienne E. Kerre , Ghent University
pp. 121
Session 5b: Reed-Muller Logic and Its Extensions

Experiments on FPRM Expressions for Partially Symmetric Logic Functions (Abstract)

V.P. Shmerko , Technical University
S.N. Yanushkevich , Technical University
G.W. Dueck , University of New Brunswick
J.T. Butler , Naval Postgraduate School
pp. 141

A New Algorithm to Compute Quaternary Reed-Muller Expansions (Abstract)

Susanto Rahardja , Nanyang Technological University
Bogdan J. Falkowski , Nanyang Technological University
pp. 153
Session 6: Invited Address
Session 7a: Logic and Algebra

De Morgan Bisemilattices (Abstract)

J.A. Brzozowski , University of Waterloo
pp. 173

Finite-Valued Approximations of Product Logic (Abstract)

Stefano Aguzzoli , ITC-IRST
Brunella Gerla , University of Milan
pp. 179

Integration of Information in Four-Valued Logics under Non-Uniform Assumptions (Abstract)

Nicolas Spyratos , Universite de Paris Sud
Daniel Stamate , Universite de Paris Sud
Yann Loyer , Universite de Paris Sud
pp. 185
Session 7b: Decision Diagrams

Lower Bound Sifting for MDDs (Abstract)

Rolf Drechsler , Albert-Ludwigs-University
Wolfgang Günther , Albert-Ludwigs-University
Dragan Jankovic , University of Nis
pp. 193

Implementation of Multiple-Output Functions Using PQMDDs (Abstract)

Tsutomu Sasao , Kyushu Institute of Technology
Munehiro Matsuura , Kyushu Institute of Technology
Yukihiro Iguchi , Meiji University
pp. 199

Fibonacci Decision Diagrams and Spectral Fibonacci Decision Diagrams (Abstract)

Karen Egiazarian , Tampere University of Technology
Jaakko Astola , Tampere University of Technology
Milena Stankovic , National Institute of Science
Radomir S. Stankovic , National Institute of Science
pp. 206
Session 8a: Circuits I

Cost-Analysis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits (Abstract)

Abdullah Al-Mutawa , Kuwait University
Mostafa Abd-El-Barr , King Fahd University of Petroleum and Minerals
pp. 215

Implementation of Multiple-Valued Multiplier on GF(3m) Using Current Mode CMOS (Abstract)

Boo Sik Shin , Ansan College
Hyeon Kyeong Seong , Institute of Induk Technology
Jai Seok Choi , Institute of Induk Technology
Heung Soo Kim , Inha University
pp. 221
Session 8b: Decision Diagrams and Test

Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions (Abstract)

Elena Dubrova , Royal Institute of Technology
Harald Sack , Universit?t Trier
Christoph Meinel , Universit?t Trier
pp. 233

Dynamic Re-Encoding During MDD Minimization (Abstract)

Wolfgang Günther , Albert-Ludwigs-University
Rolf Drechsler , Albert-Ludwigs-University
Frank Schmiedle , Albert-Ludwigs-University
pp. 239

Controllability/Observability Measures for Multiple-Valued Test Generation Based on D-Algorithm (Abstract)

Yutaka Hata , Himeji Institute of Technology
Nobuyuki Matsui , Himeji Institute of Technology
Naotake Kamiura , Himeji Institute of Technology
pp. 245
Session 9a: Evolutionary and Information Theory Approaches

Evolutionary Multi-Level Network Synthesis in Given Design Style (Abstract)

T. Luba , Warsaw University of Technology
M. Opoka , Technical University
V. Shmerko , Technical University
C. Moraga , Dortmund University,
S. Yanushkevich , Technical University
pp. 253

Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4) (Abstract)

D. Popel , Technical University,
V. Shmerko , Technical University,
S. Yanushkevich , Technical University,
pp. 265
Session 9b: Image and Language Processing

On an Architecture of Medical Image Registration System Based on Multiple-Valued Logic (Abstract)

Yuri Kitamura , Osaka University Medical School
Syoji Kobashi , Himeji Institute of Technology
Naotake Kamiura , Himeji Institute of Technology
Yutaka Hata , Himeji Institute of Technology
Toshio Yanagida , Osaka University Medical School
pp. 273

A Four-Valued Logic B(4) of E(9) for Modeling Human Communication (Abstract)

Raiek Alnakari , George Mason University
David Rine , George Mason University
pp. 285
Session 10: Invited Address

Structures with Many-Valued Information and their Relational Proof Theory (Abstract)

Ivo Düntsch , University of Ulster at Jordanstown
Wendy MacCaull , St. Francis Xavier University
Ewa Orlowska , Institute of Telecommunications
pp. 293
Session 11a: Circuits II
Session 11b: Theorem-Proving and Applications

The 2-SAT Problem of Regular Signed CNF Formulas (Abstract)

Bernhard Beckert , University of Karlsruhe
Felip Manyà , University of Lleida
Reiner Hähnle , Chalmers University of Technology
pp. 331

Chaining Techniques for Automated Theorem Proving in Many-Valued Logics (Abstract)

Harald Ganzinger , Max-Planck-Institut f?r Informatik
Viorica Sofronie-Stokkermans , Max-Planck-Institut f?r Informatik
pp. 337
Session 12: Invited Address

Properties of Independent Components of Self-Motion Optical Flow (Abstract)

Soo-Young Lee , Korea Advanced Institute of Science and Technology
Terrence J. Sejnowski , Salk Institute
Ki-Young Park , Korea Advanced Institute of Science and Technology
Marwan A. Jabri , Oregon Graduate Institute of Science and Technology and University of Sydney
pp. 355
Session 14: Invited Address

A Multilevel-Cell 32Mb Flash Memory (Abstract)

R. Alexis , Intel Corporation
M. Hensel , Intel Corporation
G. Atwood , Intel Corporation
K. Frary , Intel Corporation
P. Ruby , Intel Corporation
K. Wojciechowski , Intel Corporation
D. Mills , Intel Corporation
M. Ishac , Intel Corporation
R. Rozman , Intel Corporation
J. Javanifard , Intel Corporation
S. Sweha , Intel Corporation
M. Landgraf , Intel Corporation
D. Leak , Intel Corporation
A. Fazio , Intel Corporation
B. Baltar , Intel Corporation
M. Bauer , Intel Corporation
S. Talreja , Intel Corporation
K. Loe , Intel Corporation
pp. 367
Session 15a: Circuits III

Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch (Abstract)

K.W. Current , University of California at Davis
pp. 377
Session 15b: Clones and Asynchronous Machines

Rigidity Problem of Autodual Clones (Abstract)

Ivo G. Rosenberg , Universit? de Montr?al
Masahiro Miyakawa , Tsukuba College of Technology
pp. 391

Logic Synthesis of Controllers for B-Ternary Asynchronous Systems (Abstract)

D. Michael Miller , University of Victoria
Yasunori Nagata , University of the Ryukyus
Masao Mukaidono , Meiji University
pp. 402
Session 16: Invited Address

Silicon Single-Electron Devices and Their Applications (Abstract)

Yukinori Ono , NTT Basic Research Laboratories
Katsumi Murase , NTT Basic Research Laboratories
Yasuo Takahashi , NTT Basic Research Laboratories
Akira Fujiwara , NTT Basic Research Laboratories
pp. 411
Session 17a: Arithmetics and Systems
Session 17b: Verification and Power Estimation

A Method for Approximate Equivalence Checking (Abstract)

Mitch Thornton , Mississippi State University
Wolfgang Guenther , Albert-Ludwigs University
Rolf Drechsler , Albert-Ludwigs University
pp. 447

Probabilistic Verification of Multiple-Valued Functions (Abstract)

Elena Dubrova , Royal Institute of Technology
Harald Sack , Universit?t Trier
pp. 460

Author Index (PDF)

pp. 467
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