2013 IEEE 43rd International Symposium on Multiple-Valued Logic (1998)

Fukuoka, Japan

May 27, 1998 to May 29, 1998

ISSN: 0195-623X

ISBN: 0-8186-8371-6

TABLE OF CONTENTS

Message from the Symposium Chair (PDF)

pp. xi

Message from the Program Chair (PDF)

pp. xii

Symposium Committee (PDF)

pp. xiii

Organizing Committee (PDF)

pp. xv

Referees (PDF)

pp. xvi

Session I: Invited Address

Session IIa: Devices

A Josephson Ternary Memory Circuit (Abstract)

pp. 19

Session IIb: Cellular Array and Fault Tolerance

Session IIIa: Decision Diagrams

Session IIIb: Algebra 1

Session IVa: Logic Design 1

Session IVb: Logic

Session V: Invited Address

Session VIa: VLSI Circuits 1

Set-Valued Logic Circuits for Next Generation VLSI Architectures (Abstract)

pp. 140

Session VIb: Applications of Multiple-Valued Logic

Session VIIa: Logic Design 2

Session VIIb: Genetic Algorithms in MVL

Session VIII: Invited Address

Session IXa: Minimization

On Low Cost Realization of Multiple-Valued Logic Functions (Abstract)

pp. 233

Session IXb: Algebra 2

Functional Entropy and Decision Trees (Abstract)

pp. 257

Session Xa: VLSI Circuits 2

Session Xb: Theory of Fuzzy Logic

A Study on Operations in Interval and Paired Probabilities (Abstract)

pp. 310

Session XI: Invited Address

Session XII: Invited Address

Session XIII: Invited Address

Session XIVa: Applications of Fuzzy Logic

A Proposal and an Application of a Career-Mode Membership Function (Abstract)

pp. 344

Session XIVb: Clone Theory

On Partial Clones Containing All Idempotent Partial Operations (Abstract)

pp. 369

Index of Authors (PDF)

pp. 383