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2013 IEEE 43rd International Symposium on Multiple-Valued Logic (1995)
Bloomington, Indiana
May 23, 1995 to May 25, 1995
ISBN: 0-8186-7118-1
TABLE OF CONTENTS

Committees (PDF)

pp. xi
Session 1: VLSI

A High-Speed Interconnect Network Using Ternary Logic (Abstract)

J.K. Madsen , Center for Broadband Telecommun., Tech. Univ. Denmark, Lyngby, Denmark
S.I. Long , Center for Broadband Telecommun., Tech. Univ. Denmark, Lyngby, Denmark
pp. 0002

Wire-Free Computing Circuits Using Optical Wave-Casting (Abstract)

T. Higuchi , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
T. Aoki , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
S. Sakurai , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
pp. 0008

Redundant Complex Number Systems (Abstract)

T. Higuchi , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
Y. Ohi , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
T. Aoki , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
pp. 0014

Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices (Abstract)

M. Kameyama , Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan
M. Ryu , Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan
pp. 0020
Session 2: Logic Design I

Planar Multiple-Valued Decision Diagrams (Abstract)

T. Sasao , Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
J.T. Butler , Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
pp. 0028

Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation (Abstract)

Z. Zilic , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Z.G. Vranesic , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 0036

Properties of the Zhang-Watari Transform (Abstract)

C. Moraga , Dept. of Comput. Sci., Dortmund Univ., Germany
R. Oenning , Dept. of Comput. Sci., Dortmund Univ., Germany
pp. 0044
Session 3: Circuit Design I

Memory Circuits for Multiple-Valued Logic Voltage Signals (Abstract)

K.W. Current , Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
pp. 0052

From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators (Abstract)

K. Navi , Univ. de Paris-Sud, Orsay, France
D. Etiemble , Univ. de Paris-Sud, Orsay, France
pp. 0058

Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic (Abstract)

M. Kameyama , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
A. Mochizuki , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
T. Hanyu , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
pp. 0064
Session 4: Algebra I

The Radii of Sheffer Functions Over E(3) (Abstract)

J. Beckman , Graduate Sch., City Univ. of New York, NY, USA
T.C. Wesselkamper , Graduate Sch., City Univ. of New York, NY, USA
pp. 0072

Classification of Functions and Enumeration of Bases of Set Logic under Boolean Compositions (Abstract)

C. Reischer , Dept. of Comput. Sci., Ottawa Univ., Ont., Canada
A. Ngom , Dept. of Comput. Sci., Ottawa Univ., Ont., Canada
I. Stojmenovic , Dept. of Comput. Sci., Ottawa Univ., Ont., Canada
pp. 0078
Session 5: Device-Based Circuit and Testing I

Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems (Abstract)

M. Kameyama , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
Xiaowei Deng , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
T. Hanyu , Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
pp. 0092

Random Pattern Fault Simulation in Multi-Valued Circuits (Abstract)

R. Krieger , Dept. of Comput. Sci., Frankfurt Univ., Germany
R. Drechsler , Dept. of Comput. Sci., Frankfurt Univ., Germany
B. Becker , Dept. of Comput. Sci., Frankfurt Univ., Germany
pp. 0098

The Evaluation of Full Sensitivity for Test Generation in MVL Circuits (Abstract)

D.B. Gurov , Dept. of Comput. Sci., Victoria Univ., BC, Canada
E.V. Dubrova , Dept. of Comput. Sci., Victoria Univ., BC, Canada
J.C. Muzio , Dept. of Comput. Sci., Victoria Univ., BC, Canada
pp. 0104
Session 6: Logic I

Paraconsistent Circumscription: First-Order Case (Abstract)

Zuoquan Lin , Comput. Sci. Dept., Shantou Univ., Guangdong, China
pp. 0112

Novel Quantized Transform for Ternary Systems (Abstract)

B.J. Falkowski , Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
S. Rahardja , Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
pp. 0117

A Three-Valued Semantics for Discourse Representations (Abstract)

Y. Nakayama , Comput. Logic Lab., Teikyo Heisei Univ., Chiba, Japan
S. Akama , Comput. Logic Lab., Teikyo Heisei Univ., Chiba, Japan
pp. 0123
Invited Address
Session 7: Fuzzy Logic

On the Mutual Definability of Fuzzy Tolerance Relations and Fuzzy Tolerance Coverings (Abstract)

H. Thiele , Dept. of Comput. Sci. 1, Dortmund Univ., Germany
pp. 0140

On Lattice-Isomorphism Between Fuzzy Equivalence Relations and Fuzzy Partitions (Abstract)

N. Schmechel , Dept. of Comput. Sci. 1, Dortmund Univ., Germany
pp. 0146

Segment Matrix Vector Quantization and Fuzzy Logic for Isolated-Word Speech Recognition (Abstract)

Zhijian Li , Inst. of Microelectron., Tsinghua Univ., Beijing, China
Bingxue Shi , Inst. of Microelectron., Tsinghua Univ., Beijing, China
Liusheng Liu , Inst. of Microelectron., Tsinghua Univ., Beijing, China
pp. 0152
Session 8: Logic Design II

Efficient Algorithm for the Generation of Fixed Polarity Quaternary Reed-Muller Expansions (Abstract)

B.J. Falkowski , Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
S. Rahardia , Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
pp. 0158

Factorization of Multi-Valued Logic Functions (Abstract)

J.E. Chen , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Hui Min Wang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 0164

On Input Permutation Technique for Multiple-Valued Logic Synthesis (Abstract)

K. Yamato , Dept. of Comput. Eng., Himeji Inst. of Technol., Japan
N. Kamiura , Dept. of Comput. Eng., Himeji Inst. of Technol., Japan
Y. Hata , Dept. of Comput. Eng., Himeji Inst. of Technol., Japan
pp. 0170
Session 9: Device-Based Circuit and Testing II

The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors (Abstract)

Wang Shoujue , Inst. of Semicond., Acad. Sinica, Beijing, China
Feng Hongjuan , Inst. of Semicond., Acad. Sinica, Beijing, China
Wu Xunwei , Inst. of Semicond., Acad. Sinica, Beijing, China
pp. 0178

A Fuzzy Membership Function Circuit Using Hysteretic Resonant Tunneling Diodes (Abstract)

Hung Chang Lin , Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
Hao Tang , Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
pp. 0182

On Designing of 4-Valued Memory with Double-Gate TFT (Abstract)

Horng Nan Chern , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Hui Min Wang , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Min Shung Liao , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Chung Len Lee , Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
pp. 0187
Session 10: Algebra II

Join-Irreducible Clones of Multiple-Valued Logic Algebra (Abstract)

G. Pogosyan , Div. of Natural Sciences, Int. Christian Univ., Tokyo, Japan
A. Nozaki , Div. of Natural Sciences, Int. Christian Univ., Tokyo, Japan
pp. 0194

Finitary Approximations and Metric Structure of the Space of Clones (Abstract)

H. Machida , Dept. of Math., Hitotsubashi Univ., Tokyo, Japan
pp. 0200

Finite Algebraic Models for Residuated Logic (Abstract)

W. MacCaull , Dept. of Math. & Comput. Sci., St. Francis Xavier Univ., Antigonish, NS, Canada
pp. 0206
Session 11: Circuit Design II

Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm (Abstract)

R.J. Bolton , Canadian Microelectron. Corp., Queen's Univ., Kingston, Ont., Canada
M.H. Abd-El-Barr , Canadian Microelectron. Corp., Queen's Univ., Kingston, Ont., Canada
A.K. Jain , Canadian Microelectron. Corp., Queen's Univ., Kingston, Ont., Canada
pp. 0216

Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits (Abstract)

Xunwei Wu , Dept. of Electron. Eng., Hangzhou Univ., China
Xiexiong Chen , Dept. of Electron. Eng., Hangzhou Univ., China
Jizhong Shen , Dept. of Electron. Eng., Hangzhou Univ., China
pp. 0222

2^k-ary Cyclic AN Codes for Burst Error Correction (Abstract)

Y. Ohkura , Fac. of Eng., Tokushima Univ., Japan
R. Murakami , Fac. of Eng., Tokushima Univ., Japan
R. Shimada , Fac. of Eng., Tokushima Univ., Japan
pp. 0228
Session 12: Logic II

A Characterization of Kleenean Functions (Abstract)

M. Mukaidono , Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan
H. Kikuchi , Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan
N. Takagi , Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan
K. Nakashima , Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan
pp. 0236

Uniqueness of Partially Specified Multiple-Valued Kleenean Function (Abstract)

M. Mukaidono , Dept. of Electr. Eng., Tokai Univ., Hiratsuka, Japan
N. Takagi , Dept. of Electr. Eng., Tokai Univ., Hiratsuka, Japan
S. Nakanishi , Dept. of Electr. Eng., Tokai Univ., Hiratsuka, Japan
H. Kikuchi , Dept. of Electr. Eng., Tokai Univ., Hiratsuka, Japan
pp. 0242

On Logic of Paradox (Abstract)

Wei Li , Comput. Sci. Dept., Shantou Univ., China
Zuoquan Lin , Comput. Sci. Dept., Shantou Univ., China
pp. 0248
Invited Address

Decomposition of Multiple-Valued Functions (Abstract)

T. Luba , Inst. of Telecommun., Warsaw Univ. of Technol., Poland
pp. 0256
Session 13: Artificial Intelligence

Some New Results for Multiple-Valued Genetic Algorithms (Abstract)

T.C. Wesselkamper , Graduate Sch., City Univ. of New York, NY, USA
J. Danowitz , Graduate Sch., City Univ. of New York, NY, USA
pp. 0264

Learning Multiple-Valued Logic Networks Based on Back Propagation (Abstract)

Zheng Tang , Fac. of Eng., Miyazaki Univ., Japan
O. Ishizuka , Fac. of Eng., Miyazaki Univ., Japan
K. Tanno , Fac. of Eng., Miyazaki Univ., Japan
pp. 0270

Three-Valued Constructive Logic and Logic Programs (Abstract)

S. Akama , Dept. of Inf. Syst., Teikyo Heisei Univ., Chiba, Japan
pp. 0276
Session 14: Logic Design III

Functional Decision Diagrams for Multiple-Valued Functions (Abstract)

R.S. Stankovic , Brace Taskovica 17/29, Nis, Yugoslavia
pp. 0284

Multiple-Valued Logic Design Using Multiple-Valued EXOR (Abstract)

N. Kamiura , Fac. of Eng., Himeji Inst. of Technol., Japan
K. Yamato , Fac. of Eng., Himeji Inst. of Technol., Japan
A. Hozumi , Fac. of Eng., Himeji Inst. of Technol., Japan
Y. Hata , Fac. of Eng., Himeji Inst. of Technol., Japan
pp. 0290

Author Index (PDF)

pp. 0296
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