The Community for Technology Leaders
Low Power Electronics and Design, International Symposium on (2009)
San Fancisco, CA, USA
Aug. 19, 2009 to Aug. 21, 2009
ISBN: 978-1-60558-684-7
TABLE OF CONTENTS
Papers

Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic (Abstract)

Denis Flandre , Université catholique de Louvain, Louvain-la-Neuve, Belgium
Dina Kamel , Université catholique de Louvain, Louvain-la-Neuve, Belgium
Jean-Didier Legat , Université catholique de Louvain, Louvain-la-Neuve, Belgium
David Bol , Université catholique de Louvain, Louvain-la-Neuve, Belgium
pp. 3-8

Design and analysis of ultra-thin-body SOI based subthreshold SRAM (Abstract)

Vita Pi-Ho Hu , National Chiao Tung University, Hsinchu, Taiwan ROC
Ching-Te Chuang , National Chiao Tung University, Hsinchu, Taiwan ROC
Yu-Sheng Wu , National Chiao Tung University, Hsinchu, Taiwan ROC
Ming-Long Fan , National Chiao Tung University, Hsinchu, Taiwan ROC
Pin Su , National Chiao Tung University, Hsinchu, Taiwan ROC
pp. 9-14

Slew-aware clock tree design for reliable subthreshold circuits (Abstract)

Xin Zhao , Georgia Institute of Technology, Atlanta, GA, USA
Saibal Mukhopadhyay , Georgia Institute of Technology, Atlanta, GA, USA
Sung Kyu Lim , Georgia Institute of Technology, Atlanta, GA, USA
Jeremy R. Tolbert , Georgia Institute of Technology, Atlanta, GA, USA
pp. 15-20

Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits (Abstract)

David Bol , Université catholique de Louvain, Louvain-la-Neuve, Belgium
Jean-Didier Legat , Université catholique de Louvain, Louvain-la-Neuve, Belgium
Denis Flandre , Université catholique de Louvain, Louvain-la-Neuve, Belgium
pp. 21-26

Serial sub-threshold circuits for ultra-low-power systems (Abstract)

Benton H. Calhoun , University of Virginia, Charlottesville, VA, USA
Sudhanshu Khanna , University of Virginia, Charlottesville, VA, USA
pp. 27-32

Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction (Abstract)

Domenik Helms , OFFIS, D26121 Oldenburg, Germany
Wolfgang Nebel , CvO Univerity, D26121, Oldenburg, Germany
Kai Hylla , OFFIS, D26121, Oldenburg, Germany
pp. 33-38

Variation-aware supply voltage assignment for minimizing circuit degradation and leakage (Abstract)

Xiaoming Chen , Dept. of E.E., TNList, Tsinghua University, Beijing, China
Yu Cao , Dept. of E.E., Arizona State University, Tempe, USA
Yuchun Ma , Dept. of C.S., TNList, Tsinghua University, Beijing, China
Yu Wang , Dept. of E.E., TNList, Tsinghua University, Beijing, China
Huazhong Yang , Dept. of E.E., TNList, Tsinghua University, Beijing, China
pp. 39-44

A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation (Abstract)

Rahul M. Rao , IBM T. J. Watson Center, Yorktown Heights, NY, USA
Amlan Ghosh , University of Utah, Salt Lake City, UT, USA
Richard B. Brown , University of Utah, Salt Lake City, UT, USA
pp. 45-50

Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits (Abstract)

Koichi Hamamoto , Osaka University, Suita, Japan
Masanori Hashimoto , Osaka University, Suita, Japan
Takao Onoye , Osaka University, Suita, Japan
Yukio Mitsuyama , Osaka University, Suita, Japan
pp. 51-56

Statistical static timing analysis considering leakage variability in power gated designs (Abstract)

Azadeh Davoodi , University of Wisconsin - Madison, Madison, WI, USA
Abhishek Sinkar , University of Wisconsin - Madison, Madison, WI, USA
Michael J. Anderson , University of Wisconsin - Madison, Madison, WI, USA
Jungseob Lee , University of Wisconsin - Madison, Madison, WI, USA
Nam Sung Kim , University of Wisconsin - Madison, Madison, WI, USA
pp. 57-62

A low power high noise immunity boost DC-DC converter using the differential difference amplifiers (Abstract)

Liyu Yang , NC State University, Raleigh, NC, USA
Jiwei Fan , NC State University, Raleigh, NC, USA
Xin Zhou , NC State University, Raleigh, NC, USA
Alex Huang , NC State University, Raleigh, NC, USA
pp. 63-68

A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications (Abstract)

Hui Shao , The Hong Kong University of Science and Technology, Hong Kong, Hong Kong
Chi-Ying Tsui , The Hong Kong University of Science and Technology, Hong Kong, Hong Kong
Wing-Hung Ki , The Hong Kong University of Science and Technology, Hong Kong, Hong Kong
pp. 69-74

A CMOS low power current-mode polyphase filter (Abstract)

Noman Tasadduq , King Fahd University of Petroleum & Minerals, Dhahran, Saudi Arabia
Hussain Alzaher , King Fahd University of Petroleum & Minerals, Dhahran, Saudi Arabia
pp. 75-80

Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination (Abstract)

Kaushik Bhattacharyya , IIT-Kharagpur, Kharagpur, India
Pradip Mandal , IIT-Kharagpur, Kharagpur, India
Tamal Das , IIT-Kharagpur, Kharagpur, India
P.V. Ratna Kumar , IIT-Kharagpur, Kharagpur, India
pp. 81-86

Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories (Abstract)

Ken Takeuchi , University of Tokyo, Tokyo, Japan
Hiroto Nakai , Toshiba Corporation, Yokohama, Japan
Shinji Miyamoto , Toshiba Corporation, Yokohama, Japan
Takayasu Sakurai , University of Tokyo, Tokyo, Japan
Koichi Ishida , University of Tokyo, Tokyo, Japan
Tadashi Yasufuku , University of Tokyo, Tokyo, Japan
Makoto Takamiya , University of Tokyo, Tokyo, Japan
pp. 87-92

PPT: joint performance/power/thermal management of DRAM memory for multi-core systems (Abstract)

Ku-Jei King , IBM Corporation, Taipei, Taiwan ROC
Chung-Hsiang Lin , National Taiwan University, Taipei, Taiwan ROC
Chia-Lin Yang , National Taiwan University, Taipei, Taiwan ROC
pp. 93-98

Predict and act: dynamic thermal management for multi-core processors (Abstract)

Raid Zuhair Ayoub , University of California, San Diego, La Jolla, CA, USA
Tajana Simunic Rosing , University of California, San Diego, La Jolla, CA, USA
pp. 99-104

Online work maximization under a peak temperature constraint (Abstract)

X. Sharon Hu , University of Notre Dame, Notre Dame, IN, USA
Thidapat Chantem , University of Notre Dame, Notre Dame, IN, USA
Robert P. Dick , University of Michigan, Ann Arbor, MI, USA
pp. 105-110

Dynamic thermal management using thin-film thermoelectric cooling (Abstract)

Qiong Cai , Intel Barcelona Research Center, Intel Labs-UPC, Barcelona, Spain
Pedro Chaparro , Intel Barcelona Research Center, Intel Labs-UPC, Barcelona, Spain
José González , Intel, Barcelona, Spain
Greg Chrysler , Intel, Santa Clara, USA
pp. 111-116

A 2.6 (Abstract)

Travis N. Blalock , University of Virginia, Charlottesville, VA, USA
Steven C. Jocke , University of Virginia, Charlottesville, VA, USA
Benton H. Calhoun , University of Virginia, Charlottesville, VA, USA
Jonathan F. Bolus , University of Virginia, Charlottesville, VA, USA
Stuart N. Wooters , University of Virginia, Charlottesville, VA, USA
pp. 117-118

A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM (Abstract)

Chris H. Kim , University of Minnesota, Minneapolis, MN, USA
Ki Chul Chun , University of Minnesota, Minneapolis, MN, USA
Pulkit Jain , University of Minnesota, Minneapolis, MN, USA
pp. 119-120

Frequency and yield optimization using power gates in power-constrained designs (Abstract)

Abhishek Sinkar , University of Wisconsin-Madison, Madison, USA
Jun Seomun , Korea Advanced Institute of Science and Technology, Taejon, South Korea
Youngsoo Shin , Korea Advanced Institute of Science and Technology, Taejon, USA
Ken Choi , Illinois Inst. of Tech., Chicago, USA
Jungseob Lee , University of Wisconsin-Madison, Madison, USA
Nam Sung Kim , University of Wisconsin-Madison, Madison, WI, USA
Tae Hee Han , Sungkyunkwan University, Suwon, South Korea
pp. 121-126

NBTI-aware power gating for concurrent leakage and aging optimization (Abstract)

Massimo Poncino , Politecnico di Torino, Torino, Italy
Enrico Macii , Politecnico di Torino, Torino, Italy
Andrea Calimera , Politecnico di Torino, Torino, Italy
pp. 127-132

The opportunity cost of low power design: a case study in circuit tuning (Abstract)

George D. Gristede , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
Victor V. Zyuban , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
Matthew M. Ziegler , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
Joshua Friedrich , IBM Systems and Technology Group, Austin, TX, USA
Milena Vratonjic , University of California Davis, Davis, CA, USA
pp. 133-138

Behavior-level observability don't-cares and application to low-power behavioral synthesis (Abstract)

Bin Liu , Computer Science Department, UCLA, Los Angeles, CA, USA
Jason Cong , Computer Science Department, UCLA, Los Angeles, CA, USA
Zhiru Zhang , AutoESL Design Technologies, Inc., Los Angeles, CA, USA
pp. 139-144

Minimizing data center cooling and server power costs (Abstract)

Massoud Pedram , USC, Los Angeles, CA, USA
Ehsan Pakbaznia , USC, Los Angeles, CA, USA
pp. 145-150

Thinking outside the box: power management at the system level & beyond (Abstract)

Thomas F. Wenisch , University of Michigan, Ann Arbor, MI, USA
pp. 151-152

A look inside IBM's green data center research (Abstract)

John B. Carter , IBM Austin Research Laboratory, Austin, TX, USA
pp. 153-154

Sustainable IT ecosystems and data centers (Abstract)

Cullen E. Bash , Hewlett-Packard Laboratories, Palo Alto, CA, USA
pp. 155-156

Circuit design in nano-scale CMOS era: opportunities & challenges (Abstract)

Kevin Zhang , Intel Corporation, Hillsboro, OR, USA
pp. 157-158

Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy (Abstract)

Jianwei Dai , University of Connecticut, Storrs, CT, USA
Lei Wang , University of Connecticut, Storrs, CT, USA
pp. 159-164

Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches (Abstract)

Hsien-Hsin S. Lee , Georgia Tech, Atlanta, GA, USA
Mrinmoy Ghosh , ARM Inc., Austin, TX, USA
Stuart Biles , ARM Ltd., Cambridge, United Kingdom
Simon Ford , ARM Ltd., Cambridge, United Kingdom
Emre Ozer , ARM Ltd., Cambridge, United Kingdom
pp. 165-170

Energy-efficient renaming with register versioning (Abstract)

Dmitry Ponomarev , State University of New York, Binghamton, NY, USA
Hui Zeng , State University of New York, Binghamton, NY, USA
Kanad Ghose , State University of New York, Binghamton, NY, USA
Ju-Young Jung , State University of New York, Binghamton, NY, USA
pp. 171-176

Cooperative shared resource access control for low-power chip multiprocessors (Abstract)

Masaaki Kondo , The University of Electro-Communications, Chofu-shi, Tokyo, Japan
Noriko Takagi , The University of Tokyo, Meguro-ku, Tokyo, Japan
Hiroshi Sasaki , The University of Tokyo, Meguro-ku, Tokyo, Japan
Hiroshi Nakamura , The University of Tokyo, Meguro-ku, Tokyo, Japan
pp. 177-182

An energy-efficient checkpointing mechanism for out of order commit processor (Abstract)

Hui Zeng , State University of New York, Binghamton, NY, USA
Kanad Ghose , State University of New York, Binghamton, NY, USA
Matt T. Yourst , State University of New York, Binghamton, NY, USA
pp. 183-188

Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors (Abstract)

Nam Sung Kim , University of Wisconsin-Madison, Madison, WI, USA
Abhishek Sinkar , University of Wisconsin-Madison, Madison, WI, USA
pp. 189-194

Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator (Abstract)

Debabrata Mohapatra , Purdue University, West Lafayette, IN, USA
Georgios Karakonstantis , Purdue University, West Lafayette, IN, USA
Kaushik Roy , Purdue University, West Lafayette, IN, USA
pp. 195-200

Optimizing total power of many-core processors considering voltage scaling limit and process variations (Abstract)

Jungseob Lee , University of Wisconsin-Madison, Madison, WI, USA
Nam Sung Kim , University of Wisconsin-Madison, Madison, WI, USA
pp. 201-206

Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection (Abstract)

Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA, USA
Lawrence Pileggi , Carnegie Mellon University, Pittsburgh, PA, USA
Sebastian Herbert , Carnegie Mellon University, Pittsburgh, PA, USA
Alyssa Bonnoit , Carnegie Mellon University, Pittsburgh, PA, USA
pp. 207-212

Pulse width modulation for reduced peak power full-swing on-chip interconnect (Abstract)

Mackenzie R. Scott , University of California, Davis, Davis, CA, USA
Rajeevan Amirtharajah , University of California, Davis, Davis, CA, USA
pp. 213-218

Low power circuit design based on heterojunction tunneling transistors (HETTs) (Abstract)

Jin Cai , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
Isaac Lauer , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
David Blaauw , University of Michigan, Ann Arbor, MI, USA
Leland Chang , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
Steven J. Koester , IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
Daeyeon Kim , University of Michigan, Ann Arbor, MI, USA
Dennis Sylvester , University of Michigan, Ann Arbor, MI, USA
Yoonmyung Lee , University of Michigan, Ann Arbor, MI, USA
pp. 219-224

A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications (Abstract)

Sylvain Clerc , STMicroelectronics, Crolles, France
Fabian Firmin , STMicroelectronics, Crolles, France
Gilles Sicard , TIMA Laboratory, Grenoble, France
Fady Abouzeid , STMicroelectronics, Crolles, France
Marc Renaudin , TIEMPO SAS, Montbonnot-Saint-Martin, France
pp. 225-230

A low power 3D integrated FFT engine using hypercube memory division (Abstract)

Nariman Moezzi-Madani , North Carolina State University, Raleigh, NC, USA
Thorlindur Thorolfsson , North Carolina State University, Raleigh, NC, USA
Paul D. Franzon , North Carolina State University, Raleigh, NC, USA
pp. 231-236

Data manipulation techniques to reduce phase change memory write energy (Abstract)

Tong Zhang , Rensselaer Polytechnic Institute, Troy, NY, USA
Wei Xu , Rensselaer Polytechnic Institute, Troy, NY, USA
Jibang Liu , Rensselaer Polytechnic Institute, Troy, NY, USA
pp. 237-242

vGreen: a system for energy efficient computing in virtualized environments (Abstract)

Gaurav Dhiman , UC San Diego, La Jolla, CA, USA
Giacomo Marchetti , UC San Diego, La Jolla, CA, USA
Tajana Rosing , UC San Diego, La Jolla, CA, USA
pp. 243-248

Near optimal battery-aware energy management (Abstract)

Goran Konjevod , Arizona State University, Tempe, AZ, USA
Karam S. Chatha , Arizona State University, Tempe, AZ, USA
Sushu Zhang , Arizona State University, Tempe, AZ, USA
pp. 249-254

Transaction-based adaptive dynamic voltage scaling for interactive applications (Abstract)

Yao Guo , Peking University
Xia Zhao , Peking University
Xiangqun Chen , Peking University
pp. 255-260

Tracking the power in an enterprise decision support system (Abstract)

Justin Meza , HP Labs, Palo Alto, CA, USA
Mehul A. Shah , HP Labs, Palo Alto, CA, USA
Parthasarathy Ranganathan , HP Labs, Palo Alto, CA, USA
Judson Veazey , Hewlett-Packard BCS, Ft. Collins, CO, USA
Mike Fitzner , Hewlett-Packard BCS, Redmond, WA, USA
pp. 261-266

Ranking servers based on energy savings for computation offloading (Abstract)

Karthik Kumar , Purdue University, West Lafayette, IN, USA
Yung-Hsiang Lu , Purdue University, West Lafayette, IN, USA
Yamini Nimmagadda , Purdue University, West Lafayette, IN, USA
pp. 267-272

Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era (Abstract)

Kiyoo Itoh , Hitachi, Ltd.,, Kokubunji, Tokyo, Japan
pp. 273-274

Non volatile memories to enable system power scaling (Abstract)

Al Fazio , Intel Fellow, Director, Memory Technology Development, Technology and Manufacturing Group, , USA
pp. 275-276

Low voltage tunnel transistor architecture and its viability for energy efficient logic applications (Abstract)

Suman Datta , Pennsylvania State University, University Park, PA, USA
pp. 277-278

Reducing the leakage and timing variability of 2D ICcs using 3D ICs (Abstract)

Aung Si , Brown University, Providence, RI, USA
Sherief Reda , Brown University, Providence, RI, USA
R. Iris Bahar , Brown University, Providence, RI, USA
pp. 283-286

An optimization strategy for low energy and high performance for the on-chip interconnect signalling (Abstract)

Saeid Nooshabadi , Gwangju Institute of Science and Technology, Gwangju, South Korea
Ge Chen , University of New South Wales, Gwangju, Australia
Steven Duvall , University of New South Wales, Sydney, Australia
pp. 287-290

A high-performance low-power nanophotonic on-chip network (Abstract)

Alan R. Mickelson , University of Colorado, Boulder, CO, USA
Manish Vachharajani , University of Colorado, Boulder, CO, USA
Li Shang , University of Colorado, Boulder, CO, USA
Jie Wu , Tsinghua University, Beijing, China
Wounjhang Park , University of Colorado, Boulder, CO, USA
Zheng Li , Tsinghua University, Beijing, China
Dejan Filipovic , University of Colorado, Boulder, CO, USA
Yihe Sun , Tsinghua University, Beijing, China
pp. 291-294

Exploration of 3D stacked L2 cache design for high performance and efficient thermal control (Abstract)

Guangyu Sun , Pennsylvania State University, State College, PA, USA
Xiaoxia Wu , Pennsylvania State University, State College, PA, USA
Yuan Xie , Pennsylvania State University, State College, PA, USA
pp. 295-298

Power-management-based Chien search for low power BCH decoder (Abstract)

Q.M. Jonathan Wu , University of Windsor, Windsor, ON, Canada
Chunhong Chen , University of Windsor, Windsor, ON, Canada
Shu-Yi Wong , University of Windsor, Windsor, ON, Canada
pp. 299-302

Low power robust signal processing (Abstract)

Aarul Jain , Arizona State University, Tempe, AZ, USA
Chaitali Chakrabarti , Arizona State University, Tempe, AZ, USA
Veera Papirla , Arizona State University, Tempe, AZ, USA
pp. 303-306

Enabling ultra low voltage system operation by tolerating on-chip cache failures (Abstract)

Amin Ansari , University of Michigan, Ann Arbor, MI, USA
Scott Mahlke , University of Michigan, Ann Arbor, MI, USA
Shantanu Gupta , University of Michigan, Ann Arbor, MI, USA
Shuguang Feng , University of Michigan, Ann Arbor, MI, USA
pp. 307-310

Design of multi-mode 4-switch buck-boost controller (Abstract)

Wu Xiaobo , Zhejiang University, Hangzhou, China
Lou Jiana , Zhejiang University, Hangzhou, China
pp. 311-314

Electromigration study of power-gated grids (Abstract)

Aida Todri , University of California Santa Barbara, Santa Barbara, CA, USA
Malgorzata Marek-Sadowska , University of California Santa Barbara, Santa Barbara, CA, USA
pp. 315-318

Software-defined SIMO step-up/down power converter with adaptive global/local power allocation scheme for DVS-enabled multicore systems (Abstract)

Dongsheng Ma , The University of Arizona, Tucson, AZ, USA
Rajdeep Bondade , The University of Arizona, Tucson, AZ, USA
Feng Luo , The University of Arizona, Tucson, AZ, USA
pp. 319-322

A novel 0.5 V 15 (Abstract)

Charalambos Andreou , Chair of Microelectronics, Department of Microsystems Engineering (IMTEK), Freiburg, Germany
Dominic Maurath , Chair of Microelectronics, Department of Microsystems Engineering (IMTEK), Freiburg, Germany
Yiannos Manoli , Chair of Microelectronics, Department of Microsystems Engineering (IMTEK), Freiburg, Germany
pp. 323-326

SOI, interconnect, package, and mainboard thermal characterization (Abstract)

Jose Renau , UC Santa Cruz, Santa Cruz, CA, USA
Joseph Nayfach-Battilana , UC Santa Cruz, Santa Cruz, CA, USA
pp. 327-330

N-version temperature-aware scheduling and binding (Abstract)

Farinaz Koushanfar , Rice University, Houston, TX, USA
Yousra Alkabani , Rice University, Houston, TX, USA
Miodrag Potkonjak , UCLA, Los Angeles, CA, USA
pp. 331-334

Energy-aware instruction-set customization for real-time embedded multiprocessor systems (Abstract)

Jungsoo Kim , Dept. of EECS, Korea Advanced Institute of Science and Technology, Daejeon, South Korea
Chong-Min Kyung , Dept. of EECS, Korea Advanced Institute of Science and Technology, Daejeon, South Korea
Sangkwon Na , Dept. of EECS, Korea Advanced Institute of Science and Technology, Daejeon, South Korea
Seungrok Jung , SOC Platform Development Team, System LSI Division, Device Solution Business, Samsung Electronics, Yongin, South Korea
pp. 335-338

Power-saving color transformation of mobile graphical user interfaces on OLED-based displays (Abstract)

Lin Zhong , Rice University, Houston, TX, USA
Mian Dong , Rice University, Houston, TX, USA
Yung-Seok Kevin Choi , Rice University, Houston, TX, USA
pp. 339-342

An energy-delay efficient 2-level data cache architecture for embedded system (Abstract)

Jongmin Lee , Korea Advanced Institute of Science and Technology, Daejoen, South Korea
Soontae Kim , Korea Advanced Institute of Science and Technology, Daejoen, South Korea
pp. 343-346

Experimental analysis of sequence dependence on energy saving for error tolerant image processing (Abstract)

Se Hun Kim , Georgia Institute of Technology, Atlanta, GA, USA
Wayne Wolf , Georgia Institute of Technology, Atlanta, GA, USA
Saibal Mukohopadhyay , Georgia Institute of Technology, Atlanta, GA, USA
pp. 347-350

A programmable implementation of neural signal processing on a smartdust for brain-computer interfaces (Abstract)

Joseph Oresko , University of Pittsburgh, Pittsburgh, PA, USA
John Krais , University of Pittsburgh, Pittsburgh, PA, USA
Allen C. Cheng , University of Pittsburgh, Pittsburgh, PA, USA
Shimeng Huang , University of Pittsburgh, Pittsburgh, PA, USA
Yuwen Sun , University of Pittsburgh, Pittsburgh, PA, USA
pp. 351-354

An experimental validation of system level design space exploration methodology for energy efficient sensor nodes (Abstract)

M. Balakrishnan , Indian Institute of Technology Delhi, New Delhi, India
Sonali Chouhan , Indian Institute of Technology Delhi, New Delhi, India
Ranjan Bose , Indian Institute of Technology Delhi, New Delhi, India
pp. 355-358

It is all about power analysis, exploration and trade-offs (Abstract)

Ran Avinun , Cadence, San Jose, USA
Sandeep Mirchandani , Broadcom, San Jose, USA
Camille Kokozaki , IDT, San Jose, USA
Brian Fuller , Editor, Corte Madera, USA
Soheil Modirzadeh , Cadence, San Jose, USA
Jon McDonald , Mentor, San Jose, USA
pp. 359-360

Dealing with disaggregation in ever-changing world of semiconductors (Abstract)

Yankin Tanurhan , Virage Logic Corporation, Fremont, CA, USA
pp. 363-364

A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management (Abstract)

Joo-Young Kim , Korea Advanced Institute of Science and Technology, Daejeon, South Korea
Hoi-Jun Yoo , Korea Advanced Institute of Science and Technology, Daejeon, South Korea
Minsu Kim , Korea Advanced Institute of Science and Technology, Daejeon, South Korea
Seungjin Lee , Korea Advanced Institute of Science and Technology, Daejeon, South Korea
Jinwook Oh , Korea Advanced Institute of Science and Technology, Daejeon, South Korea
pp. 365-370

The design of a bloom filter hardware accelerator for ultra low power systems (Abstract)

Michael J. Lyons , Harvard University, Cambridge, MA, USA
David Brooks , Harvard University, Cambridge, MA, USA
pp. 371-376

Dynamic power gating with quality guarantees (Abstract)

Anita Lungu , Duke University, Durham, NC, USA
Daniel J. Sorin , Duke University, Durham, NC, USA
Alper Buyuktosunoglu , IBM, Yorktown Heights, NY, USA
Pradip Bose , IBM, Yorktown Heights, NY, USA
pp. 377-382

End-to-end validation of architectural power models (Abstract)

Stephen W. Keckler , University of Texas at Austin, Austin, TX, USA
Madhu Saravana Sibi Govindan , University of Texas at Austin, Austin, TX, USA
Doug Burger , Microsoft, Redmond, WA, USA
pp. 383-388

Low power fast and dense longest prefix match content addressable memory for IP routers (Abstract)

Lawrence T. Clark , Arizona State University, Tempe, AZ, USA
Satendra Kumar Maurya , Arizona State University, Tempe, AZ, USA
pp. 389-394

MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency (Abstract)

Xiaowei Li , Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Xiaoyao Liang , NVIDIA Corporation, Santa Clara, CA, USA
Hui Liu , Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Guihai Yan , Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Yinhe Han , Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 395-400

Adaptive RF chain management for energy-efficient spatial-multiplexing MIMO transmission (Abstract)

Lin Zhong , Rice University, Houston, TX, USA
Hang Yu , Rice University, Houston, TX, USA
Ashutosh Sabharwal , Rice University, Houston, TX, USA
pp. 401-406

Remote progressive firmware update for flash-based networked embedded systems (Abstract)

Jinsik Kim , University of California, Irvine, Irvine, CA, USA
Pai H. Chou , University of California, Irvine, Irvine, CA, USA
pp. 407-412

Power management in energy harvesting embedded systems with discrete service levels (Abstract)

Lothar Thiele , ETH, Zurich, Switzerland
Jian-Jia Chen , ETH, Zurich, Switzerland
Clemens Moser , ETH, Zurich, Switzerland
pp. 413-418

Energy efficient sampling for event detection in wireless sensor networks (Abstract)

Mani B. Srivastava , University of California, Los Angeles, Los Angeles, CA, USA
Younghun Kim , University of California, Los Angeles, Los Angeles, CA, USA
Zainul Charbiwala , University of California, Los Angeles, Los Angeles, CA, USA
Sadaf Zahedi , University of California, Los Angeles, Los Angeles, CA, USA
Jonathan Friedman , University of California, Los Angeles, Los Angeles, CA, USA
pp. 419-424

Ultra low voltage CMOS (Abstract)

Kaushik Roy , Purdue University, , USA
pp. 425-426

Emerging technologies and their impact on system design (Abstract)

Yuan Xie , Pennsylvania State University, , USA
Norm Jouppi , HP Labs, , USA
pp. 427-428

Green transistors to green architectures (Abstract)

Suman Datta , Pennsylvania State University, University Park, USA
Vijaykrishnan Narayanan , Pennsylvania State University, University Park, USA
pp. 429-430

Green at the micro-scale: towards self-powered embedded systems (Abstract)

Vijay Raghunathan , Purdue University, West Lafayette, IN, USA
pp. 431-432
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