The Community for Technology Leaders
Low Power Electronics and Design, International Symposium on (2008)
Bangalore, India
Aug. 11, 2008 to Aug. 13, 2008
ISBN: 978-1-60558-109-5
TABLE OF CONTENTS
Papers

Towards a green electronic world: a collaborative approach (Abstract)

Jaswinder Ahuja , Cadence Design Systems, Inc., Noida, India
pp. 1-2

Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits (Abstract)

Yukio Mitsuyama , Osaka University, Osaka, Japan
Masanori Hashimoto , Osaka University, Osaka, Japan
Hiroshi Fuketa , Osaka University, Osaka, Japan
Takao Onoye , Osaka University, Osaka, Japan
pp. 3-8

Optimal technology selection for minimizing energy and variability in low voltage applications (Abstract)

Mingoo Seok , University of Michigan, Ann Arbor, MI, USA
David Blaauw , University of Michigan, Ann Arbor, MI, USA
Dennis Sylvester , University of Michigan, Ann Arbor, MI, USA
pp. 9-14

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology (Abstract)

Tadao Yamanaka , Renesas Design Corp., Itami, Japan
Masanori Kurimoto , Renesas Technology Corp., Itami, Japan
Hidehiro Takata , Renesas Technology Corp., Itami, Japan
Hirofumi Shinohara , Renesas Technology Corp., Itami, Japan
Hiroshi Makino , Osaka Institute of Technology, Hirakata, Japan
Hiroaki Suzuki , Renesas Technology Corp., Itami, Japan
pp. 15-20

Enhancing beneficial jitter using phase-shifted clock distribution (Abstract)

Pulkit Jain , University of Minnesota, Minneapolis, MN, USA
Chris Kim , University of Minnesota, Minneapolis, MN, USA
Dong Jiao , University of Minnesota, Minneapolis, MN, USA
Jie Gu , University of Minnesota, Minneapolis, MN, USA
pp. 21-26

Dynamic virtual ground voltage estimation for power gating (Abstract)

Ranga Vemuri , University of Cincinnati, Cincinnati, OH, USA
Hao Xu , University of Cincinnati, Cincinnati, OH, USA
Wen-Ben Jone , University of Cincinnati, Cincinnati, OH, USA
pp. 27-32

A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops (Abstract)

Behnam Amelifard , University of Southern California, Los Angeles, CA, USA
Mohammad Ghasemazar , University of Southern California, Los Angeles, CA, USA
Massoud Pedram , University of Southern California, Los Angeles, CA, USA
pp. 33-38

Power-gating-aware high-level synthesis (Abstract)

Youngsoo Shin , KAIST, Daejeon, South Korea
Changsik Shin , KAIST, Daejeon, South Korea
Taewhan Kim , Seoul National University, Seoul, South Korea
Eunjoo Choi , LG Electronics, Seoul, South Korea
pp. 39-44

A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing (Abstract)

Azadeh Davoodi , University of Wisconsin, Madison, WI, USA
Lin Xie , University of Wisconsin, Madison, WI, USA
Tai-Hsuan Wu , University of Wisconsin, Madison, WI, USA
pp. 45-50

Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction (Abstract)

Alberto Macii , Politecnico di Torino, Torino, Italy
Massimo Poncino , Politecnico di Torino, Torino, Italy
Luca Benini , Università di Bologna, Bologna, Italy
Enrico Macii , Politecnico di Torino, Torino, Italy
Ashoka Sathanur , Politecnico di Torino, Torino, Italy
pp. 51-56

A multi-story power delivery technique for 3D integrated circuits (Abstract)

Tae-Hyoung Kim , University of Minnesota, Minneapolis, MN, USA
Chris H. Kim , University of Minnesota, Minneapolis, MN, USA
John Keane , University of Minnesota, Minneapolis, MN, USA
Pulkit Jain , University of Minnesota, Minneapolis, MN, USA
pp. 57-62

Energy harvesting photodiodes with integrated 2D diffractive storage capacitance (Abstract)

Diego R. Yankelevich , University of California, Davis, CA, USA
Rajeevan Amirtharajah , University of California, Davis, CA, USA
Travis Kleeburg , University of California, Davis, CA, USA
Nathaniel J. Guilar , University of California, Davis, CA, USA
Erin G. Fong , University of California, Davis, CA, USA
pp. 63-68

Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion (Abstract)

Magdy A. Bayoumi , University of Louisiana at Lafayette, Lafayette, LA, USA
Charbel J. Akl , University of Louisiana at Lafayette, Lafayette, LA, USA
pp. 69-74

Low-power high-accuracy timing systems for efficient duty cycling (Abstract)

Young H. Cho , University of California, Los Angeles, Los Angeles, CA, USA
Jonathan Friedman , University of California, Los Angeles, Los Angeles, CA, USA
Mani B. Srivastava , University of California, Los Angeles, Los Angeles, CA, USA
Zainul Charbiwala , University of California, Los Angeles, Los Angeles, CA, USA
Thomas Schmid , University of California, Los Angeles, Los Angeles, CA, USA
pp. 75-80

An expected-utility based approach to variation aware VLSI optimization under scarce information (Abstract)

Nagarajan Ranganathan , University of South Florida, Tampa, FL, USA
Upavan Gupta , University of South Florida, Tampa, FL, USA
pp. 81-86

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes (Abstract)

Weiping Shi , Texas A&M University, College Station, TX, USA
Rajiv Joshi , IBM, Yorktown Heights, TX, USA
Sani Nassif , IBM, Austin, TX, USA
Zhuo Li , IBM, Austin, TX, USA
Ying Zhou , Texas A&M University, College Station, TX, USA
Hung Ngo , IBM, Austin, TX, USA
Rouwaida Kanj , IBM, Austin, TX, USA
JB Kuang , IBM, Austin, TX, USA
pp. 87-92

Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation (Abstract)

Tohru Ishihara , Kyushu University, Fukuoka, Japan
Maziar Goudarzi , Kyushu University, Fukuoka, Japan
pp. 93-98

Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power (Abstract)

Koustav Bhattacharya , University of South Florida, Tampa, FL, USA
Nagarajan Ranganathan , University of South Florida, Tampa, FL, USA
pp. 99-104

Variation-aware gate sizing and clustering for post-silicon optimized circuits (Abstract)

David Blaauw , University of Michigan, Ann Arbor, USA
Dennis Sylvester , University of Michigan, Ann Arbor, USA
Cheng Zhuo , University of Michigan, Ann Arbor, USA
pp. 105-110

Error-resilient low-power Viterbi decoders (Abstract)

Rami A. Abdallah , University of Illinois at Urbana Champaign, Urbana, IL, USA
Naresh R. Shanbhag , University of Illinois at Urbana Champaign, Urbana, IL, USA
pp. 111-116

Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators (Abstract)

Makoto Takamiya , University of Tokyo, Tokyo, Japan
Koichi Ishida , University of Tokyo, Tokyo, Japan
Taro Niiyama , University of Tokyo, Tokyo, Japan
Zhe Piao , University of Tokyo, Tokyo, Japan
Masami Murakata , STARC, Yokohama, Japan
Takayasu Sakurai , University of Tokyo, Tokyo, Japan
pp. 117-122

Thermal analysis of 8-T SRAM for nano-scaled technologies (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN, USA
Jaydeep P. Kulkarni , Purdue University, West Lafayette, IN, USA
Mesut Meterelliyoz , Purdue University, West Lafayette, IN, USA
pp. 123-128

Analyzing static and dynamic write margin for nanometer SRAMs (Abstract)

Jiajing Wang , University of Virginia, Charlottesville, VA, USA
Satyanand Nalam , University of Virginia, Charlottesville, VA, USA
Benton H. Calhoun , University of Virginia, Charlottesville, VA, USA
pp. 129-134

Power management solutions for computer systems and datacenters (Abstract)

Charles Lefurgy , IBM Austin Research Lab, Austin, TX, USA
Tom Keller , IBM Austin Research Lab, Austin, TX, USA
Heather Hanson , IBM Austin Research Lab, Austin, TX, USA
Juan Rubio , IBM Austin Research Lab, Austin, TX, USA
Karthick Rajamani , IBM Austin Research Lab, Austin, TX, USA
Soraya Ghiasi , IBM Austin Research Lab, Austin, TX, USA
pp. 135-136

Low power design under parameter variations (Abstract)

Kaushik Roy , Purdue University, West Lafayette, IN, USA
Swarup Bhunia , Case Western Reserve University, Cleveland, OH, USA
pp. 137-138

Caching for bursts (C-Burst): let hard disks sleep well and work energetically (Abstract)

Feng Chen , The Ohio State University, Columbus, OH, USA
Xiaodong Zhang , The Ohio State University, Columbus, OH, USA
pp. 141-146

3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding (Abstract)

Lars Bauer , University of Karlsruhe, Karlsruhe, Germany
Muhammad Shafique , University of Karlsruhe, Karlsruhe, Germany
Jörg Henkel , University of Karlsruhe, Karlsruhe, Germany
pp. 147-152

Energy conservation by adaptive feature loading for mobile content-based image retrieval (Abstract)

Yu-Ju Hong , Purdue University, West Lafayette, IN, USA
Karthik Kumar , Purdue University, West Lafayette, IN, USA
Yamini Nimmagadda , Purdue University, West Lafayette, IN, USA
Yung-Hsiang Lu , Purdue University, West Lafayette, IN, USA
pp. 153-158

Extending the lifetime of media recorders constrained by battery and flash memory size (Abstract)

Chaitali Chakrabarti , Arizona State University, Tempe, AZ, USA
Younghyun Kim , Seoul National University, Seoul, South Korea
Nam Ik Cho , Seoul National University, Seoul, South Korea
Youngjin Cho , Seoul National University, Seoul, South Korea
Naehyuck Chang , Seoul National University, Seoul, South Korea
pp. 159-164

Proactive temperature management in MPSoCs (Abstract)

Tajana Simunic Rosing , UC San Diego, La Jolla, CA, USA
Ayse Kivilcim Coskun , UC San Diego, La Jolla, CA, USA
Kenny C. Gross , Sun Microsystems, San Diego, CA, USA
pp. 165-170

Entry control in network-on-chip for memory power reduction (Abstract)

Kiyoung Choi , Seoul National University, Seoul, South Korea
Dongwook Lee , Seoul National University, Seoul, South Korea
Sungjoo Yoo , POSTECH, Pohang, South Korea
pp. 171-176

PowerAntz: distributed power sharing strategy for network on chip (Abstract)

Suman Kalyan Mandal , Texas A&M University, College Station, TX, USA
Rabi N. Mahapatra , Texas A&M University, College Station, TX, USA
pp. 177-182

System implications of integrated photonics (Abstract)

Norman P. Jouppi , Hewlett-Packard, Palo Alto, CA, USA
pp. 183-184

Design of dual threshold voltages asynchronous circuits (Abstract)

Hossein Pedram , Amirkabir University of Technology, Tehran, Iran
Behnam Ghavami , Amirkabir University of Technology, Tehran, Iran
pp. 185-188

O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors (Abstract)

Jung-Hwan Choi , Purdue University, West Lafayette, IN, USA
Kaushik Roy , Purdue University, West Lafayette, IN, USA
Swaroop Ghosh , Purdue University, West Lafayette, IN, USA
Patrick Ndai , Purdue University, West Lafayette, IN, USA
pp. 189-192

Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensation (Abstract)

Chetan D. Parikh , Dhirubhai Ambani Inst. of Information & Communication Tech., Gandhinagar, India
Raju Kunde , Dhirubhai Ambani Inst. of Information & Communication Tech., Gandhinagar, India
Vineet Kumar Singh , Dhirubhai Ambani Inst. of Information & Communication Tech., Gandhinagar, India
Shagun Bajoria , Dhirubhai Ambani Inst. of Information & Communication Tech., Gandhinagar, India
pp. 193-196

Single stage static level shifter design for subthreshold to I/O voltage conversion (Abstract)

Dennis M. Sylvester , University of Michigan, Ann Arbor, MI, USA
Yi-Shiang Lin , University of Michigan, Ann Arbor, MI, USA
pp. 197-200

Power reduction in on-chip interconnection network by serialization (Abstract)

Bharadwaj Amrutur , Indian Institute of Science, Bangalore, India
Madan Arvind , Indian Institute of Science, Bangalore, India
pp. 201-204

A probabilistic technique for full-chip leakage estimation (Abstract)

Qing Wu , Binghamton University, State University of New York, Binghamton, NY, USA
Qinru Qiu , Binghamton University, State University of New York, Binghamton, NY, USA
Shaobo Liu , Binghamton University, State University of New York, Binghamton, NY, USA
pp. 205-208

Bus encoding for simultaneous delay and energy optimization (Abstract)

Qinru Qiu , Binghamton University, State University of New York, Binghamton, NY, USA
Qing Wu , Binghamton University, State University of New York, Binghamton, NY, USA
Jingyi Zhang , Binghamton University, State University of New York, Binghamton, NY, USA
pp. 209-212

Frequency planning for multi-core processors under thermal constraints (Abstract)

Michael Kadin , Brown University, Providence, RI, USA
Sherief Reda , Brown University, Providence, RI, USA
pp. 213-216

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits (Abstract)

R. Iris Bahar , Brown University, Providence, RI, USA
Massimo Poncino , Politecnico di Torino, Torino, Italy
Enrico Macii , Politecnico di Torino, Torino, Italy
Andrea Calimera , Politecnico di Torino, Torino, Italy
pp. 217-220

Variability of flip-flop timing at sub-threshold voltages (Abstract)

Niklas Lotze , University of Freiburg, Freiburg, Germany
Yiannos Manoli , University of Freiburg, Freiburg, Germany
Maurits Ortmanns , University of Freiburg, Freiburg, Germany
pp. 221-224

Low power current mode receiver with inductive input impedance (Abstract)

Dinesh Sharma , Indian Institute of Technology, Bombay, Mumbai, India
Marshnil Dave , Indian Institute of Technology, Bombay, Mumbai, India
Maryam Shojaei Baghini , Indian Institute of Technology, Bombay, Mumbai, India
pp. 225-228

Analytical results for design space exploration of multi-core processors employing thread migration (Abstract)

Sarma Vrudhula , Arizona State University, Tempe, AZ, USA
Ravishankar Rao , Arizona State University, Tempe, AZ, USA
Krzysztof Berezowski , Arizona State University, Tempe, AZ, USA
pp. 229-232

A physical level study and optimization of CAM-based checkpointed register alias table (Abstract)

Elham Safi , University of Toronto, Toronto, ON, Canada
Andreas Moshovos , University of Toronto, Toronto, ON, Canada
Andreas Veneris , University of Toronto, Toronto, ON, Canada
pp. 233-236

A tutorial on test power (Abstract)

Vishwani D. Agrawal , Auburn University, Auburn, AL, USA
pp. 237-238

Power delivery for high performance microprocessors (Abstract)

Srikanth Balasubramanian , Intel Corporation, Bangalore, India
pp. 239-240

Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension (Abstract)

Kazuaki Murakami , Kyushu University, Fukuoka, Japan
Koji Inoue , Kyushu University, Fukuoka, Japan
Hamid Noori , Institute of Systems, Information Technologies and Nanotechnologies, Fukuoka, Japan
Farhad Mehdipour , Kyushu University, Fukuoka, Japan
pp. 241-246

Energy-efficient MESI cache coherence with pro-active snoop filtering for multicore microprocessors (Abstract)

Avadh Patel , State University of New York, Binghamton, NY, USA
Kanad Ghose , State University of New York, Binghamton, NY, USA
pp. 247-252

A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes (Abstract)

Jie Jin , The Hong Kong University of Science and Technology, Kowloon, Hong Kong
Chi-Ying Tsui , The Hong Kong University of Science and Technology, Kowloon, Hong Kong
pp. 253-258

A secure and low-energy logic style using charge recovery approach (Abstract)

Alireza Ejlali , Sharif University of Technology, Tehran, Iran
Mohammad T. Manzuri Shalmani , Sharif University of Technology, Tehran, Iran
Mehrdad Khatir , Sharif University of Technology, Tehran, Iran
Mahmoud Salmasizadeh , Sharif University of Technology, Tehran, Iran
Amir Moradi , Sharif University of Technology, Tehran, Iran
pp. 259-264

Word-interleaved cache: an energy efficient data cache architecture (Abstract)

T. Venkata Kalyan , IIIT Hyderabad, Hyderabad, India
Madhu Mutyam , Indian Institute of Technology Madras, Madras, India
pp. 265-270

Optimal power and noise allocation for analog and digital sections of a low power radio receiver (Abstract)

Bharadwaj S. Amrutur , Indian Institute of Science, Bangalore, India
Manodipan Sahoo , Indian Institute of Science, Bangalore, India
Satyam Dwivedi , Indian Institute of Science, Bangalore, India
Navakanta Bhat , Indian Institute of Science, Bangalore, India
Kannan Aryaperumal Sankaragomathi , Indian Institute of Science, Bangalore, India
pp. 271-276

Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies (Abstract)

Xuning Chen , Princeton University, Princeton, NJ, USA
Gu-Yeon Wei , Harvard University, Cambridge, MA, USA
Li-Shiuan Peh , Princeton University, Princeton, NJ, USA
pp. 277-282

On the power efficiency of cascode compensation over Miller compensation in two-stage operational amplifiers (Abstract)

Hamed Aminzadeh , Ferdowsi University of Mashhad, Mashhad, Iran
Khalil Mafinezhad , Ferdowsi University of Mashhad, Mashhhad, Iran
pp. 283-288

A 1-V piecewise curvature-corrected CMOS bandgap reference (Abstract)

Yong-sheng Wang , Harbin Institute of Technology, Harbin, China
Yu-nan Fu , Harbin Institute of Technology, Harbin, China
Jing-hu Li , Harbin Institute of Technology, Harbin, China
pp. 289-294

A 1.8/2.4-ghz dualband cmos low noise amplifier using miller capacitance tuning (Abstract)

Roy Paily , IIT Guwahati, Guwahati, India
Depak Balemarthy , IIT Guwahati, Guwahati, India
pp. 295-300

Innovations to extend CMOS nano-transistors to the limit (Abstract)

Tahir Ghani , Intel Corporation, Hillsboro, OR, USA
pp. 301-302

Penalty for power reduction -: performance or schedule or yield? (Abstract)

Arijit Dutta , Freescale Semiconductors, Bangalore, India
Jaswinder Ahuja , Cadence Design Systems (I) Pvt Ltd, Delhi, India
Srinath D. , Kawasaki Micro, Bangalore, India
Jayant Lahiri , ARM India, Bangalore, India
Bodhisatya Sarker , Cadence Design Systems (I) Pvt Ltd, Delhi, India
Kaip Sridhar , Marvel Technologies, Bangalore, India
Radhakrishnan Nair , SanDisk India, Bangalore, India
pp. 303-304

SOC designs in the energy conscious era (Abstract)

Srikanth Jadcherla , Synopsys Inc., Mountain View, CA, USA
pp. 305-306

Clock gating for power optimization in ASIC design cycle theory & practice (Abstract)

Udayakumar H , Texas Instruments, Bangalore, India
Jithendra Srinivas , Texas Instruments, Bangalore, India
Parimala Vishwanath , Texas Instruments, Bangalore, Iceland
Jairam S , Texas Instruments, Bangalore, India
Jagdish Rao , Texas Instruments, Bangalore, India
Madhusudan Rao , Texas Instruments, Bangalore, India
pp. 307-308

Simultaneous optimization of battery-aware voltage regulator scheduling with dynamic voltage and frequency scaling (Abstract)

Naehyuck Chang , Seoul National University, Seoul, South Korea
Kyungsoo Lee , Seoul National University, Seoul, South Korea
Younghyun Kim , Seoul National University, Seoul, South Korea
Youngjin Cho , Seoul National University, Seoul, South Korea
Yongsoo Joo , Seoul National University, Seoul, South Korea
pp. 309-314

Expected system energy consumption minimization in leakage-aware DVS systems (Abstract)

Jian-Jia Chen , Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland
Lothar Thiele , Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland
pp. 315-320

Hybrid dynamic thermal management based on statistical characteristics of multimedia applications (Abstract)

Eun Jung Kim , Texas A&M University, College Station, TX, USA
Inchoon Yeo , Texas A&M University, College Station, TX, USA
pp. 321-326

Advances in low power verification (Abstract)

Janick Bergeron , Synopsys, Inc., Mountain View, CA, USA
pp. 327-328

A framework for energy consumption based design space exploration for wireless sensor nodes (Abstract)

M. Balakrishnan , Indian Institute of Technology Delhi, New Delhi, India
Ranjan Bose , Indian Institute of Technology Delhi, New Delhi, India
Sonali Chouhan , Indian Institute of Technology Delhi, New Delhi, India
pp. 329-334

Full-system chip multiprocessor power evaluations using FPGA-based emulation (Abstract)

Gilberto Contreras , Princeton University, Princeton, NJ, USA
Abhishek Bhattacharjee , Princeton University, Princeton, NJ, USA
Margaret Martonosi , Princeton University, Princeton, NJ, USA
pp. 335-340

Noninvasive leakage power tomography of integrated circuits by compressive sensing (Abstract)

Farinaz Koushanfar , Rice University, Houston, USA
Petros Boufounos , Rice University, Houston, USA
Davood Shamsi , Rice University, Houston, USA
pp. 341-346

Low power chips: a fabless asic perspective (Abstract)

Vamsi Boppana , Open-Silicon, Inc., Milpitas, USA
Shashank Bhonge , Open-Silicon Research Pvt. Ltd, Bangalore, India
pp. 347-348

On leakage currents: sources and reduction for transistors, gates, memories and digital systems (Abstract)

Domenik Helms , OFFIS, Oldenburg, Germany
Wolfgang Nebel , University of Oldenburg, Oldenurg, Germany
pp. 349-350

Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures (Abstract)

Niranjan Soundararajan , The Pennsylvania State University, University Park, PA, USA
Narayanan Vijaykrishnan , The Pennsylvania State University, University Park, PA, USA
Anand Sivasubramaniam , The Pennsylvania State University, University Park, PA, USA
pp. 351-356

Instruction-driven clock scheduling with glitch mitigation (Abstract)

Gu-Yeon Wei , Harvard University, Cambridge, MA, USA
Xiaoyao Liang , Harvard University, Cambridge, MA, USA
Ali Durlov Khan , Harvard University, Cambridge, MA, USA
David Brooks , Harvard University, Cambridge, MA, USA
pp. 357-362

Thread fusion (Abstract)

Pedro Chaparro , UPC-Intel Lab Barcelona, Barcelona, Spain
Antonio González , UPC-Intel Lab Barcelona, Barcelona, Spain
Ryan Rakvic , United States Naval Academy, Annapolis, Annapolis, MD, USA
Qiong Cai , UPC-Intel Lab Barcelona, Barcelona, Spain
José González , UPC-Intel Lab Barcelona, Barcelona, Spain
Grigorios Magklis , UPC-Intel Lab Barcelona, Barcelona, Spain
pp. 363-368

Power-efficient clustering via incomplete bypassing (Abstract)

Mithuna S. Thottethodi , Purdue University, West Lafayette, IN, USA
DaeHo Seo , Purdue University, West Lafayette, IN, USA
Eric P. Villasenor , Purdue University, West Lafayette, IN, USA
pp. 369-374

Lazy instruction scheduling: keeping performance, reducing power (Abstract)

Mahmud Taghizadeh , Sharif University of Technology, Tehran, Iran
Ali Mahjur , Shahid Beheshti University, Tehran, Iran
Amir Hossein Jahangir , Sharif University of Technology, Tehran, Iran
pp. 375-380

On the rules of low-power design (and how to break them) (Abstract)

Todd M. Austin , University of Michigan, Ann Arbor, MI, USA
pp. 381-382

Next-generation power-aware design (Abstract)

Takayasu Sakurai , The University of Tokyo, Tokyo, Japan
pp. 383-384
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