The Community for Technology Leaders
Low Power Electronics and Design, International Symposium on (2007)
Portland, OR, USA
Aug. 27, 2007 to Aug. 29, 2007
ISBN: 978-1-59593-709-4
TABLE OF CONTENTS
Papers

Compact modeling of carbon nanotube transistor for early stage process-design exploration (Abstract)

Asha Balijepalli , Arizona State University
Saurabh Sinha , Arizona State University
Yu Cao , Arizona State University
pp. 2-7

Low power FPGA design using hybrid CMOS-NEMS approach (Abstract)

Yu Zhou , Case Western Reserve University
Shijo Thekkel , Case Western Reserve University
Swarup Bhunia , Case Western Reserve University
pp. 14-19

Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies (Abstract)

Saibal Mukhopadhyay , IBM T. J. Watson Research Center
Keunwoo Kim , IBM T. J. Watson Research Center
Ching-Te Chuang , IBM T. J. Watson Research Center
pp. 20-25

Clocking structures and power analysis for nanomagnet-based logic devices (Abstract)

M. Niemier , University of Notre Dame
M. Alam , University of Notre Dame
X. S. Hu , University of Notre Dame
G. Bernstein , University of Notre Dame
W. Porod , University of Notre Dame
M. Putney , University of Notre Dame
J. DeAngelis , University of Notre Dame
pp. 26-31

Energy efficient near-threshold chip multi-processing (Abstract)

Bo Zhai , University of Michigan
Ronald G. Dreslinski , University of Michigan
David Blaauw , University of Michigan
Trevor Mudge , University of Michigan
Dennis Sylvester , University of Michigan
pp. 32-37

Analysis of dynamic voltage/frequency scaling in chip-multiprocessors (Abstract)

Sebastian Herbert , Carnegie Mellon University
Diana Marculescu , Carnegie Mellon University
pp. 38-43

Evaluating design tradeoffs in on-chip power management for CMPs (Abstract)

Joseph Sharkey , Assured Information Security: Inc.
Alper Buyuktosunoglu , IBM TJ Watson Research Center
Pradip Bose , IBM TJ Watson Research Center
pp. 44-49

A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches (Abstract)

Sungjune Youn , LG Electronics Inc.
Hyunhee Kim , Seoul National University
Jihong Kim , Seoul National University
pp. 56-61

A robust edge encoding technique for energy-efficient multi-cycle interconnect (Abstract)

Jae-sun Seo , University of Michigan
Dennis Sylvester , University of Michigan
David Blaauw , University of Michigan
Himanshu Kaul , Intel Corporation
Ram Krishnamurthy , Intel Corporation
pp. 68-73

Sleep transistor sizing and control for resonant supply noise damping (Abstract)

Jie Gu , University of Minnesota
Hanyong Eom , University of Minnesota
Chris H. Kim , University of Minnesota
pp. 80-85

Thermal-aware methodology for repeater insertion in low-power VLSI circuits (Abstract)

Ja Chun Ku , Northwestern University
Yehea Ismail , Northwestern University
pp. 86-91

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs (Abstract)

Chi-Feng Li , National Taiwan University
Ping-Hung Yuh , National Taiwan University
Chia-Lin Yang , National Taiwan University
Yao-Wen Chang , National Taiwan University
pp. 92-97

Power optimal MTCMOS repeater insertion for global buses (Abstract)

Hanif Fatemi , Univerisity of Southern California
Behnam Amelifar , Univerisity of Southern California
Massoud Pedram , Univerisity of Southern California
pp. 98-103

Timing-driven row-based power gating (Abstract)

Ashoka Sathanur , Politecnico di Torino
Antonio Pullini , Politecnico di Torino
Luca Benini , Universita di Bologna
Alberto Macii , Politecnico di Torino
Enrico Macii , Politecnico di Torino
Massimo Poncino , Politecnico di Torino
pp. 104-109

Early power grid verification under circuit current uncertainties (Abstract)

Imad A. Ferzli , University of Toronto
Farid N. Najm , University of Toronto
Lars Kruse , Magma Design Automation
pp. 116-121

Towards a software approach to mitigate voltage emergencies (Abstract)

Meeta Sharma Gupta , Harvard University
Krishna K. Rangan , Harvard University
Michael D. Smith , Harvard University
Gu-Yeon Wei , Harvard University
David Brooks , Harvard University
pp. 123-128

Improving disk reuse for reducing power consumption (Abstract)

Mahmut Kandemir , The Pennsylvania State University
Seung Woo Son , The Pennsylvania State University
Mustafa Karakoy , Imperial College
pp. 129-134

PVS: passive voltage scaling for wireless sensor networks (Abstract)

Youngjin Cho , Seoul National University
Younghyun Kim , Seoul National University
Naehyuck Chang , Seoul National University
pp. 135-140

Voltage- and ABB-island optimization in high level synthesis (Abstract)

Domenik Helms , OFFIS research institute
Olaf Meyer , OFFIS research institute
Marko Hoyer , OFFIS research institute
Wolfgang Nebel , University of Oldenburg
pp. 153-158

Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies (Abstract)

Simone Medardoni , ENDIF - University of Ferrara
Davide Bertozzi , ENDIF - University of Ferrara
Enrico Macii , Politecnico di Torino
pp. 159-164

Power signal processing: a new perspective for power analysis and optimization (Abstract)

Quming Zhou , Rice University
Lin Zhong , Rice University
Kartik Mohanram , Rice University
pp. 165-170

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM (Abstract)

Jaydeep P. Kulkarni , Purdue University
Keejong Kim , Purdue University
Kaushik Roy , Purdue University
pp. 171-176

A low-power SRAM using bit-line charge-recycling technique (Abstract)

Keejong Kim , Purdue University
Hamid Mahmoodi , San Francisco State University
Kaushik Roy , Purdue University
pp. 177-182

Minimizing power dissipation during write operation to register files (Abstract)

Kimish Patel , University of Southern California
Wonbok Lee , University of Southern California
Massoud Pedram , University of Southern California
pp. 183-188

An on-chip NBTI sensor for measuring PMOS threshold voltage degradation (Abstract)

John Keane , University of Minnesota
Tae-Hyoung Kim , University of Minnesota
Chris H. Kim , University of Minnesota
pp. 189-194

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI (Abstract)

Yiran Chen , Seagate Technology
Hai Li , Seagate Technology
Jing Li , Purdue University
Cheng-Kok Koh , Purdue University
pp. 195-200

Throughput of multi-core processors under thermal constraints (Abstract)

Ravishankar Rao , Arizona State University
Sarma Vrudhula , Arizona State University
Chaitali Chakrabarti , Arizona State University
pp. 201-206

Dynamic voltage frequency scaling for multi-tasking systems using online learning (Abstract)

Gaurav Dhiman , University of California, San Diego
Tajana Simunic Rosing , University of California, San Diego
pp. 207-212

Thermal-aware task scheduling at the system software level (Abstract)

Jeonghwan Choi , IBM T.J. Watson Research center, Yortown Heights, NY
Chen-Yong Cher , IBM T.J. Watson Research center, Yortown Heights, NY
Hubertus Franke , IBM T.J. Watson Research center, Yortown Heights, NY
Henrdrik Hamann , IBM T.J. Watson Research center, Yortown Heights, NY
Alan Weger , IBM T.J. Watson Research center, Yortown Heights, NY
Pradip Bose , IBM T.J. Watson Research center, Yortown Heights, NY
pp. 213-218

Thermal response to DVFS: analysis with an Intel Pentium M (Abstract)

Heather Hanson , University of Texas at Austin
Stephen W. Keckler , University of Texas at Austin
Soraya Ghiasi , IBM Austin Research
Karthick Rajamani , IBM Austin Research
Freeman Rawson , IBM Austin Research
Juan Rubio , IBM Austin Research
pp. 219-224

Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules (Abstract)

Sushu Zhang , Arizona State University
Karam S. Chatha , Arizona State University
Goran Konjevod , Arizona State University
pp. 225-230

Low power soft-output signal detector design for wireless MIMO communication systems (Abstract)

Sizhong Chen , Rensselaer Polytechnic Institute
Tong Zhang , Rensselaer Polytechnic Institute
pp. 232-237

A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices (Abstract)

Jeong-Ho Woo , KAIST
Ju-Ho Sohn , KAIST
Hyejung Kim , KAIST
Jongcheol Jeong , Corelogic, Inc.,Samsungdong, Kangnumgu, Seoul
Euljoo Jeong , Corelogic, Inc.,Samsungdong, Kangnumgu, Seoul
Suk Joong Lee , Corelogic, Inc.,Samsungdong, Kangnumgu, Seoul
Hoi-Jun Yoo , KAIST
pp. 238-243

An architecture for energy efficient sphere decoding (Abstract)

Ravi Jenkal , North Carolina State University
Rhett Davis , North Carolina State University
pp. 244-249

On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing (Abstract)

Yang Liu , Rensselaer Polytechnic Institute
Tong Zhang , Rensselaer Polytechnic Institute
pp. 250-255

Low-power H.264/AVC baseline decoder for portable applications (Abstract)

Ke Xu , The Chinese University of Hong Kong
Chiu Sing Choy , The Chinese University of Hong Kong
pp. 256-261

A 0.4-V UWB baseband processor (Abstract)

Vivienne Sze , Massachusetts Institute of Technology
Anantha P. Chandrakasan , Massachusetts Institute of Technology
pp. 262-267

Resource area dilation to reduce power density in throughput servers (Abstract)

Michael D. Powell , Intel Massachusetts, Inc.
T. N. Vijaykumar , Purdue University
pp. 268-273

Locality-driven architectural cache sub-banking for leakage energy reduction (Abstract)

Olga Golubeva , Politecnico di Torino
Mirko Loghi , Politecnico di Torino
Enrico Macii , Politecnico di Torino
Massimo Poncino , Politecnico di Torino
pp. 274-279

A multi-model power estimation engine for accuracy optimization (Abstract)

Felipe Klein , Institute of Computing, UNICAMP, Brazil
G. Araujo , Institute of Computing, UNICAMP, Brazil
Rodolfo Azevedo , Institute of Computing, UNICAMP, Brazil
Roberto Leao , Computer Sciences Department, UFSC, Brazil
Luiz C. V. dos Santos , Computer Sciences Department, UFSC, Brazil
pp. 280-285

A micro power management system and maximum output power control for solar energy harvesting applications (Abstract)

Hui Shao , The Hong Kong University of Science and Technology
Chi-Ying Tsui , The Hong Kong University of Science and Technology
Wing-Hung Ki , The Hong Kong University of Science and Technology
pp. 298-303

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor (Abstract)

David E. Duarte , Intel Corporation
Greg Taylor , Intel Corporation
Keng L. Wong , Intel Corporation
Usman Mughal , Intel Corporation
George Geannopoulos , Intel Corporation
pp. 304-309

Single inductor, multiple input, multiple output (SIMIMO) power mixer-charger-supply system (Abstract)

Min Chen , Georgia Tech Analog, Power, and Energy IC Research Lab
Gabriel A. Rincón-Mora , Georgia Tech Analog, Power, and Energy IC Research Lab
pp. 310-315

Vibration energy scavenging and management for ultra low power applications (Abstract)

Lu Chao , Hong Kong University of Science and Technology
Chi Ying Tsui , Hong Kong University of Science and Technology
Wing Hung Ki , Hong Kong University of Science and Technology
pp. 316-321

Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source (Abstract)

Jianli Zhuo , Arizona State University
Chaitali Chakrabarti , Arizona State University
Naehyuck Chang , Seoul National University
pp. 322-327

Design of an efficient power delivery network in an soc to enable dynamic power management (Abstract)

Behnam Amelifard , University of Southern California
Massoud Pedram , University of Southern California
pp. 328-333

Energy-efficient and performance-enhanced disks using flash-memory cache (Abstract)

Jen-Wei Hsieh , National Chiayi University
Tei-Wei Kuo , National Taiwan University
Po-Liang Wu , National Taiwan University
Yu-Chung Huang , Genesys Logic: Inc.
pp. 334-339

SAPP: scalable and adaptable peak power management in nocs (Abstract)

Praveen S. Bhojwani , Texas A&M University
Jason D. Lee , Texas A&M University
Rabi N. Mahapatra , Texas A&M University
pp. 340-345

All watts considered (Abstract)

pp. 346

A 65-nm pulsed latch with a single clocked transistor (Abstract)

Martin Saint-Laurent , QUALCOMM Incorporated
Baker Mohammad , QUALCOMM Incorporated
Paul Bassett , QUALCOMM Incorporated
pp. 347-350

A methodology for analysis and verification of power gated circuits with correlated results (Abstract)

Aveek Sarkar , Apache Design Solutions
Shen Lin , Apache Design Solutions
Kai Wang , Apache Design Solutions
pp. 351-354

Vt balancing and device sizing towards high yield of sub-threshold static logic gates (Abstract)

Yu Pu , Technische Universiteit Eindhoven
Henk Corporaal , Technische Universiteit Eindhoven
Yajun Ha , National University of Singapore
pp. 355-358

Power-efficient LDPC code decoder architecture (Abstract)

Kazunori Shimizu , Waseda University
Nozomu Togawa , Waseda University
Takeshi Ikenaga , Waseda University
Satoshi Goto , Waseda University
pp. 359-362

Reducing cache energy consumption by tag encoding in embedded processors (Abstract)

Mingming Zhang , Chinese Academy of Sciences
Xiaotao Chang , Chinese Academy of Sciences
Ge Zhang , Chinese Academy of Sciences
pp. 367-370

On reducing energy-consumption by late-inserting instructions into the issue queue (Abstract)

Enric Morancho , Universitat Politècnica de Catalunya
José María Llabería , Universitat Politècnica de Catalunya
Àngel Olivé , Universitat Politècnica de Catalunya
pp. 371-374

Power-aware operand delivery (Abstract)

Erika Gunadi , University of Wisconsin
Mikko H. Lipasti , University of Wisconsin
pp. 375-378

On the latency, energy and area of checkpointed, superscalar register alias tables (Abstract)

Elham Safi , University of Toronto
Patrick Akl , University of Toronto
Andreas Moshovos , University of Toronto
Andreas Veneris , University of Toronto
Aggeliki Arapoyianni , University of Athens
pp. 379-382

Electromigration and voltage drop aware power grid optimization for power gated ICs (Abstract)

Aida Todri , University of California Santa Barbara
Malgorzata Marek-Sadowska , University of California Santa Barbara
pp. 391-394

Reducing display power in DVS-enabled handheld systems (Abstract)

Jung-hi Min , Yonsei University
Hojung Cha , Yonsei University
pp. 395-398

Phase-aware adaptive hardware selection for power-efficient scientific computations (Abstract)

Konrad Malkowski , The Pennsylvania State University
Padma Raghavan , The Pennsylvania State University
Mahmut Kandemir , The Pennsylvania State University
Mary Jane Irwin , The Pennsylvania State University
pp. 403-406

Signoff power methodology for contactless smartcards (Abstract)

Julien Mercier , STMicroelectronics
Christian Dufaza , University Provence
Mathieu Lisart , STMicroelectronics
pp. 407-410
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