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Low Power Electronics and Design, International Symposium on (2004)
Newport Beach, California, USA
Aug. 9, 2004 to Aug. 11, 2004
ISBN: 1-58113-929-2
TABLE OF CONTENTS
Keynote

Why Hot Chips are No Longer "Cool" (PDF)

Ray Bryant , IBM Systems & Technology Group
pp. 1
Session 1: Circuit Challenges for Scaled Technologies

Leakage Power Reduction by Dual-Vth Designs Under Probabilistic Analysis of Vth Variation (Abstract)

Michael Liu , University of Texas at Austin
Wei-Shen Wang , University of Texas at Austin
Michael Orshansky , University of Texas at Austin
pp. 2-7

Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS (Abstract)

Hari Ananthan , Purdue University, West Lafayette, IN
Chris H. Kim , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 8-13

Technology Exploration for Adaptive Power and Frequency Scaling in 90nm CMOS (Abstract)

Maurice Meijer , Philips Research Laboratories, Eindhoven, The Netherlands
Francesco Pessolano , Philips Research Laboratories, Eindhoven, The Netherlands
Jos? Pineda de Gyvez , Philips Research Laboratories, Eindhoven, The Netherlands
pp. 14-19

Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode (Abstract)

Suhwan Kim , Seoul National Univestiy, Korea
Stephen V. Kosonocky , IBM Thomas J. Watson Research Center, Yorktown Heights, New York
Daniel R. Knebel , IBM Thomas J. Watson Research Center, Yorktown Heights, New York
Kevin Stawiasz , IBM Thomas J. Watson Research Center, Yorktown Heights, New York
pp. 20-25
Session 2: Microarchitecural Techniques for Power Reduction

Improved Clock-Gating through Transparent Pipelining (Abstract)

Hans M. Jacobson , IBM T.J. Watson Research Center, Yorktown, NY
pp. 26-31

Microarchitectural Techniques for Power Gating of Execution Units (Abstract)

Zhigang Hu , IBM T. J. Watson Research Center
Alper Buyuktosunoglu , IBM T. J. Watson Research Center
Viji Srinivasan , IBM T. J. Watson Research Center
Victor Zyuban , IBM T. J. Watson Research Center
Hans Jacobson , IBM T. J. Watson Research Center
Pradip Bose , IBM T. J. Watson Research Center
pp. 32-37

SEPAS: A Highly Accurate Energy-Efficient Branch Predictor (Abstract)

Amirali Baniasadi , University of Victoria
Andreas Moshovos , University of Toronto
pp. 38-43

Understanding the Energy Efficiency of Simultaneous Multithreading (Abstract)

Yingmin Li , University of Virginia
David Brooks , Harvard University
Zhigang Hu , IBM T.J. Watson Research Center
Kevin Skadron , University of Virginia
Pradip Bose , IBM T.J. Watson Research Center
pp. 44-49
Poster Session 1: Cache and Bus Design

Impact of Technology Scaling on Energy Aware Execution Cache-Based Microarchitectures (Abstract)

Emil Talpes , Carnegie Mellon University, Pittsburgh, PA
Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
pp. 50-53

Design and Implementation of Correlating Caches (Abstract)

Arindam Mallik , Northwestern University, Evanston, IL
Matthew C. Wildrick , Northwestern University, Evanston, IL
Gokhan Memik , Northwestern University, Evanston, IL
pp. 58-61

Dynamic Power Management for Streaming Data (Abstract)

Nathaniel Pettis , Purdue University
Le Cai , Purdue University
Yung-Hsiang Lu , Purdue University
pp. 62-65

Delayed Line Bus Scheme: A Low-Power Bus Scheme for Coupled On-Chip Buses (Abstract)

Maged Ghoneima , Northwestern University, Evanston, IL
Yehea Ismail , Northwestern University, Evanston, IL
pp. 66-69
Poster Session 2: System Design Methodologies

Delay Optimal Low-Power Circuit Clustering for FPGAs with Dual Supply Voltages (Abstract)

Deming Chen , University of California, Los Angeles
Jason Cong , University of California, Los Angeles
pp. 70-73

Creating a Power-Aware Structured ASIC (Abstract)

R. Reed Taylor , Carnegie Mellon University, Pittsburgh, PA
Herman Schmit , Carnegie Mellon University, Pittsburgh, PA
pp. 74-77

Dynamic Voltage Scaling for Systemwide Energy Minimization in Real-Time Embedded Systems (Abstract)

Ravindra Jejurikar , University of California, Irvine
Rajesh Gupta , University of California, San Diego
pp. 78-81

ESACW: An Adaptive Algorithm For Transmission Power Reduction In Wireless Networks (Abstract)

Hang Su , Zhejiang University, Hangzhou, China
Peiliang Qiu , Zhejiang University, Hangzhou, China
Qinru Qiu , State University of New York, Binghamton, NY
pp. 82-85

Any-time Probabilistic Switching Model using Bayesian Networks (Abstract)

Shiva Shankar Ramani , University of South Florida, Tampa, Florida
Sanjukta Bhanja , University of South Florida, Tampa, Florida
pp. 86-89
Session 3: Technologies and Devices for Low-Power

Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits (Abstract)

Benton H. Calhoun , Massachusetts Institute of Technology, Cambridge, MA
Anantha Chandrakasan , Massachusetts Institute of Technology, Cambridge, MA
pp. 90-95

Device Optimization for Ultra-Low Power Digital Sub-Threshold Operation (Abstract)

Bipul C. Paul , Purdue University, West Lafayette, IN
Arijit Raychowdhury , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 96-101

Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device (Abstract)

Keunwoo Kim , IBM T. J. Watson Research Center, Yorktown Heights, NY
Koushik K. Das , IBM T. J. Watson Research Center, Yorktown Heights, NY
Rajiv V. Joshi , IBM T. J. Watson Research Center, Yorktown Heights, NY
Ching-Te Chuang , IBM T. J. Watson Research Center, Yorktown Heights, NY
pp. 102-107
Session 4: Power Optimizations for Cache Memory

Location Cache: A Low-Power L2 Cache System (Abstract)

Rui Min , University of Cincinnati, OH
Wen-Ben Jone , University of Cincinnati, OH
Yiming Hu , University of Cincinnati, OH
pp. 120-125

A Way-Halting Cache for Low-Energy High-Performance Systems (Abstract)

Chuanjun Zhang , University of California, Riverside
Frank Vahid , University of California, Riverside; UC Irvine
Jun Yang , University of California, Riverside
Walid Najjar , University of California, Riverside
pp. 126-131

Soft Error and Energy Consumption Interactions: A Data Cache Perspective (Abstract)

Lin Li , Pennsylvania State University, University Park
Vijay Degalahal , Pennsylvania State University, University Park
N. Vijaykrishnan , Pennsylvania State University, University Park
Mahmut Kandemir , Pennsylvania State University, University Park
Mary Jane Irwin , Pennsylvania State University, University Park
pp. 132-137
Session 5: Leakage Analysis and Optimization

Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion (Abstract)

Pietro Babighian , Politecnico di Torino, Italy
Luca Benini , Universit? di Bologna, Italy
Alberto Macii , Politecnico di Torino, Italy
Enrico Macii , Politecnico di Torino, Italy
pp. 138-143

Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing (Abstract)

W. Hung , The Pennsylvania State University
Y. Xie , The Pennsylvania State University
N. Vijaykrishnan , The Pennsylvania State University
M. Kandemir , The Pennsylvania State University
M. J. Irwin , The Pennsylvania State University
Y. Tsai , The Pennsylvania State University
pp. 144-149

Active Mode Leakage Reduction Using Fine-Grained Forward Body Biasing Strategy (Abstract)

Vishal Khandelwal , University of Maryland at College Park
Ankur Srivastava , University of Maryland at College Park
pp. 150-155

A Probabilistic Framework to Estimate Full-Chip Subthreshold Leakage Power Distribution Considering Within-Die and Die-to-Die P-T-V Variations (Abstract)

Songqing Zhang , University of California, Santa Barbara, CA
Vineet Wason , University of California, Santa Barbara, CA
Kaustav Banerjee , University of California, Santa Barbara, CA
pp. 156-161
Session 6: Power Supply, Voltage, and Frequency Management

Maximizing Efficiency of Solar-Powered Systems by Load Matching (Abstract)

Dexin Li , University of California, Irvine
Pai H. Chou , University of California, Irvine
pp. 162-167

Power Utility Maximization for Multiple-Supply Systems by a Load-Matching Switch (Abstract)

Chulsung Park , University of California, Irvine
Pai H. Chou , University of California, Irvine
pp. 168-173

Dynamic Voltage and Frequency Scaling based on Workload Decomposition (Abstract)

Kihwan Choi , University of Southern California, Los Angeles
Ramakrishna Soma , University of Southern California, Los Angeles
Massoud Pedram , University of Southern California, Los Angeles
pp. 174-179

Architecting Voltage Islands in Core-Based System-on-a-Chip Designs (Abstract)

Jingcao Hu , Carnegie Mellon University, Pittsburgh, PA
Youngsoo Shin , IBM T. J. Watson Research Center, Yorktown Heights, NY
Nagu Dhanwada , IBM EDA Laboratory, Hopewell Junction, NY
Radu Marculescu , Carnegie Mellon University, Pittsburgh, PA
pp. 180-185

Balanced Energy Optimization (PDF)

John Cornish , ARM, Cambridge, UK
pp. 186
Session 7: Power-efficient Bus Design

Approaches to Run-Time and Standby Mode Leakage Reduction in Global Buses (Abstract)

Rahul Rao , University of Michigan, Ann Arbor, MI
Kanak Agarwal , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
Richard Brown , University of Michigan, Ann Arbor, MI
Kevin Nowka , Austin Research Laboratories, IBM, Austin, TX
Sani Nassif , Austin Research Laboratories, IBM, Austin, TX
pp. 188-193

Spatial Encoding Circuit Techniques for Peak Power Reduction of On-Chip High-Performance Buses (Abstract)

Himanshu Kaul , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
Mark Anders , Circuit Research Labs, Intel Corporation, Hillsboro, OR
Ram Krishnamurthy , Circuit Research Labs, Intel Corporation, Hillsboro, OR
pp. 194-199

A New Algorithm for Improved VDD Assignment in Low Power Dual VDD Systems (Abstract)

Sarvesh H. Kulkarni , University of Michigan, Ann Arbor, MI
Ashish N. Srivastava , University of Michigan, Ann Arbor, MI
Dennis Sylvester , University of Michigan, Ann Arbor, MI
pp. 200-205

Limited Intra-Word Transition Codes: An Energy-Efficient Bus Encoding for LCD Display Interfaces (Abstract)

Sabino Salerno , Politecnico di Torino, Italy
Alberto Bocca , Politecnico di Torino, Italy
Enrico Macii , Politecnico di Torino, Italy
Massimo Poncino , Universit? di Verona, Italy
pp. 206-211
Session 8: High Level Power Modeling and Analysis

Microarchitectural Power Modeling Techniques for Deep Sub-Micron Microprocessors (Abstract)

Nam Sung Kim , Intel Labs, Hillsboro, OR
Taeho Kgil , University of Michigan, Ann Arbor, MI
Valeria Bertacco , University of Michigan, Ann Arbor, MI
Todd Austin , University of Michigan, Ann Arbor, MI
Trevor Mudge , University of Michigan, Ann Arbor, MI
pp. 212-217

Power-Optimal Pipelining in Deep Submicron Technology (Abstract)

Seongmoo Heo , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Krste Asanovic , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
pp. 218-223

Application-Level Prediction of Battery Dissipation (Abstract)

Chandra Krintz , University of California, Santa Barbara
Ye Wen , University of California, Santa Barbara
Rich Wolski , University of California, Santa Barbara
pp. 224-229

Minimizing Power Consumption and Complexity in a Programmable Transmit Filter Bank for OFDM (Abstract)

Alireza Mehrnia , University of California, Los Angeles
Babak Daneshrad , University of California, Los Angeles
pp. 230-235
Poster Session 3: Circuit Technologies

On Optimality of Adiabatic Switching in MOS Energy-Recovery Circuit (Abstract)

Baohua Wang , The University of Michigan, Ann Arbor, MI
Pinaki Mazumder , The University of Michigan, Ann Arbor, MI
pp. 236-239

Constant-Load Energy Recovery Memory for Efficient High-Speed Operation (Abstract)

Joohee Kim , University of Michigan, Ann Arbor
Marios C. Papaefthymiou , University of Michigan, Ann Arbor
pp. 240-243

A Comparative Study of MOS VCOs for Low Voltage High Performance Operation (Abstract)

J. H. C. Zhan , Cornell University, Ithaca, New York
J. S. Duster , Cornell University, Ithaca, New York
K. T. Kornegay , Cornell University, Ithaca, New York
pp. 244-247

A CPL-Based Dual Supply 32-bit ALU for Sub 180nm CMOS Technologies (Abstract)

Bhaskar Chatterjee , University of Waterloo, Canada
Manoj Sachdev , University of Waterloo, Canada
Ram Krishnamurthy , Intel Corp., Hillsboro, OR
pp. 248-251
Session 9: Low Power Converter Circuits

A Low-Power Rail-to-Rail 6-bit Flash ADC Based on a Novel Complementary Average-Value Approach (Abstract)

Hui-Chin Tseng , National Cheng Kung University, Tainan, Taiwan
Chi-Sheng Lin , National Cheng Kung University, Tainan, Taiwan
Hsin-Hung Ou , National Cheng Kung University, Tainan, Taiwan
Bin-Da Liu , National Cheng Kung University, Tainan, Taiwan
pp. 252-256

Integrated Adaptive DC/DC Conversion with Adaptive Pulse-Train Technique for Low-Ripple Fast-Response Regulation (Abstract)

Chuang Zhang , Louisiana State University, Baton Rouge, LA
Dongsheng Ma , University of Arizona,Tucson, AZ
Ashok Srivastava , Louisiana State University, Baton Rouge, LA
pp. 257-262

Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation (Abstract)

Gerhard Schrom , Circuit Research, Intel Labs.
Peter Hazucha , Circuit Research, Intel Labs.
Jae-Hong Hahn , Mobile Platforms Group, Intel
Volkan Kursun , University of Rochester, NY
Donald Gardner , Circuit Research, Intel Labs.
Siva Narendra , Circuit Research, Intel Labs.
Tanay Karnik , Circuit Research, Intel Labs.
Vivek De , Circuit Research, Intel Labs.
pp. 263-268

2.45 GHz Power and Data Transmission for a Low-Power Autonomous Sensors Platform (Abstract)

Stefano Gregori , University of Texas at Dallas
Yunlei Li , University of Texas at Dallas
Huijuan Li , University of Texas at Dallas
Jin Liu , University of Texas at Dallas
Franco Maloberti , University of Texas at Dallas; University of Pavia, Italy
pp. 269-273
Embedded Tutorial 1

Managing Standby and Active Mode Leakage Power in Deep Sub-micron Design (Abstract)

Lawrence T. Clark , University of New Mexico, Albuquerque, NM
Rakesh Patel , Intel Corp., Chandler, AZ
Timothy S. Beatty , Intel Corp., Chandler, AZ
pp. 274-279
Session 10: Circuits for Low Power Wireless

Architectures for Low Power Ultra-Wideband Radio Receivers in the 3.1-5GHz Band for Data Rates < 10Mbps (Abstract)

Marian Verhelst , Katholieke Universiteit Leuven, Belgium
Wim Vereecken , Katholieke Universiteit Leuven, Belgium
Michiel Steyaert , Katholieke Universiteit Leuven, Belgium
Wim Dehaene , Katholieke Universiteit Leuven, Belgium
pp. 280-285

Low-Power Asynchronous Viterbi Decoder for Wireless Applications (Abstract)

Mohamed Kawokgy , University of Toronto, Canada
C. Andr? T. Salama , University of Toronto, Canada
pp. 286-289

A CMOS Even Harmonic Mixer with Current Reuse For Low Power Applications (Abstract)

Ming-Feng Huang , National Chung Cheng University, Taiwan
Shuenn-Yuh Lee , National Chung Cheng University, Taiwan
Chung J. Kuo , National Chung Cheng University, Taiwan
pp. 290-295

A Novel Continuous-Time Common-Mode Feedback for Low-Voltage Switched-OPAMP (Abstract)

M. Ali-Bakhshian , Sharif University of Tech., Iran
K. Sadeghi , Sharif University of Tech., Iran
pp. 296-300
Session 11: Power Efficient Design for Arithmetic Circuits

The Design of a Low Power Asynchronous Multiplier (Abstract)

Yijun Liu , The University of Manchester, UK
Steve Furber , The University of Manchester, UK
pp. 301-306

Low-Power Fixed-Width Array Multipliers (Abstract)

Jinn-Shyan Wang , Chung-Cheng University, Taiwan
Chien-Nan Kuo , Chung-Cheng University, Taiwan
Tsung-Han Yang , Chung-Cheng University, Taiwan
pp. 307-312

Low-Power Carry-Select Adder Using Adaptive Supply Voltage Based on Input Vector Patterns (Abstract)

Hiroaki Suzuki , Renesas Technology Corporation, Japan
Woopyo Jeong , Purdue University, West Lafayette, IN
Kaushik Roy , Purdue University, West Lafayette, IN
pp. 313-318

Reducing Pipeline Energy Demands with Local DVS and Dynamic Retiming (Abstract)

Seokwoo Lee , The University of Michigan, Ann Arbor, MI
Shidhartha Das , The University of Michigan, Ann Arbor, MI
Toan Pham , The University of Michigan, Ann Arbor, MI
Todd Austin , The University of Michigan, Ann Arbor, MI
David Blaauw , The University of Michigan, Ann Arbor, MI
Trevor Mudge , The University of Michigan, Ann Arbor, MI
pp. 319-324
Plenary Talk II

Understanding Nanoscale Conductors (PDF)

Supriyo Datta , Purdue University, W. Lafayette, IN
pp. 325
Session 12: Energy Efficient Architectural Techniques

Mitigating Inductive Noise in SMT Processors (Abstract)

Wael El-Essawy , University of Rochester
David H. Albonesi , University of Rochester
pp. 332-337

Energy-Aware Demand Paging on NAND Flash-based Embedded Storages (Abstract)

Chanik Park , Samsung Electronics Co.
Jeong-Uk Kang , Korea Advanced Institute of Science and Technology (KAIST)
Seon-Yeong Park , Korea Advanced Institute of Science and Technology (KAIST)
Jin-Soo Kim , Korea Advanced Institute of Science and Technology (KAIST)
pp. 338-343

Application Adaptive Energy Efficient Clustered Architectures (Abstract)

Diana Marculescu , Carnegie Mellon University, Pittsburgh, PA
pp. 344-349
Embedded Tutorial 2

The Impact of Variability on Power (PDF)

Sani R. Nassif , IBM Austin Research Laboratory, Austin, TX
pp. 350
Session 13: Wireless Application Drivers for Low-Power Systems

Reducing Radio Energy Consumption of Key Management Protocols for Wireless Sensor Networks (Abstract)

Bo-Cheng Charles Lai , University of California, Los Angeles
David D. Hwang , University of California, Los Angeles
Sungha Pete Kim , Samsung Electronics Co., LTD.
Ingrid Verbauwhede , University of California, Los Angeles
pp. 351-356

Evaluating and Optimizing Power Consumption of Anti-Collision Protocols for Applications in RFID Systems (Abstract)

Feng Zhou , Fudan University, Shanghai, China
Chunhong Chen , University of Windsor, Ontario, Canada
Dawei Jin , Fudan University, Shanghai, China
Chenling Huang , Fudan University, Shanghai, China
Hao Min , Fudan University, Shanghai, China
pp. 357-362

Experience With A Low Power Wireless Mobile Computing Platform (Abstract)

Vijay Raghunathan , University of California, Los Angeles
Trevor Pering , Intel Research, Santa Clara, CA
Roy Want , Intel Research, Santa Clara, CA
Alex Nguyen , Intel Research, Santa Clara, CA
Peter Jensen , Georgia Institute of Technology, Atlanta, GA
pp. 363-368

FSM-Based Power Modeling of Wireless Protocols: the Case of Bluetooth (Abstract)

Luca Negri , Politecnico di Milano
David Macii , ALaRI - Lugano
Mariagiovanna Sami , Politecnico di Milano
Alessandra Terranegra , ALaRI - Lugano
pp. 369-374
Session 14: Adaptive Voltage Scaling

Efficient Adaptive Voltage Scaling System Through On-Chip Critical Path Emulation (Abstract)

Mohamed Elgebaly , University of Waterloo, Canada
Manoj Sachdev , University of Waterloo, Canada
pp. 375-380

An Efficient Voltage Scaling Algorithm for Complex SoCs with Few Number of Voltage Modes (Abstract)

Bita Gorjiara , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
Pai Chou , University of California, Irvine
pp. 381-386

Memory-Aware Energy-Optimal Frequency Assignment for Dynamic Supply Voltage Scaling (Abstract)

Youngjin Cho , Seoul National University, Korea
Naehyuck Chang , Seoul National University, Korea
pp. 387-392

Preemption-Aware Dynamic Voltage Scaling in Hard Real-Time Systems (Abstract)

Woonseok Kim , Seoul National University, Korea
Jihong Kim , Seoul National University, Korea
Sang Lyul Min , Seoul National University, Korea
pp. 393-398

Author Index (PDF)

pp. 399-400
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