2010 International Symposium on Electronic System Design (2010)

Bhubaneswar, Orissa India

Dec. 20, 2010 to Dec. 22, 2010

ISBN: 978-0-7695-4294-2

pp: 85-90

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISED.2010.25

ABSTRACT

In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nano technology and optical computing. Reversible logic circuits provide less power dissipation as well as distinct output assignment for each distinct input. The classical set of gates such as the NAND, AND, NOR, OR, XOR and XNOR are not reversible. This paper aims at finding a reversible counterpart of all the irreversible basic logic gates and developing full custom layout of all these gates with reversibility using 0.25µm technology to synthesize as well as simulate them to check their correctness. Attempts have been taken to minimize the circuit of all the logic gates using CMOS while making them reversible. Further the reversible logic has been utilized to design the reversible full adder and half adder. Using those gates, 4-bit Binary Parallel Adder and 4x4 multiplier circuit are also designed. Thus, this paper provides the initial threshold to building of more complex system which can execute more complicated operations using reversible logic.

INDEX TERMS

Reversible Gate, CMOS implementation, basic gates, Arithmetic circuits

CITATION

Ajit Kumar Panda,
M. Suresh,
Jagannath Satpathy,
Madhusmita Mahapatro,
Sisira Kanta Panda,
M. K. Sukla,
Meraj Saheel,
"Design of Arithmetic Circuits Using Reversible Logic Gates and Power Dissipation Calculation",

*2010 International Symposium on Electronic System Design*, vol. 00, no. , pp. 85-90, 2010, doi:10.1109/ISED.2010.25SEARCH