2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) (2016)

Seoul, South Korea

June 18, 2016 to June 22, 2016

ISSN: 1063-6897

ISBN: 978-1-4673-8948-8

pp: 570-582

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISCA.2016.56

ABSTRACT

Due to the end of supply voltage scaling and the increasing percentage of dark silicon in modern integrated circuits, researchers are looking for new scalable ways to get useful computation from existing silicon technology. In this paper we present a reconfigurable analog accelerator for solving systems of linear equations. Commonly perceived downsides of analog computing, such as low precision and accuracy, limited problem sizes, and difficulty in programming are all compensated for using methods we discuss. Based on a prototyped analog accelerator chip we compare the performance and energy consumption of the analog solver against an efficient digital algorithm running on a CPU, and find that the analog accelerator approach may be an order of magnitude faster and provide one third energy savings, depending on the accelerator design. Due to the speed and efficiency of linear algebra algorithms running on digital computers, an analog accelerator that matches digital performance needs a large silicon footprint. Finally, we conclude that problem classes outside of systems of linear equations may hold more promise for analog acceleration.

INDEX TERMS

Computer architecture, Acceleration, Mathematical model, Analog computers, Silicon, Differential equations, Embedded systems

CITATION

Y. Huang, N. Guo, M. Seok, Y. Tsividis and S. Sethumadhavan, "Evaluation of an Analog Accelerator for Linear Algebra,"

*2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)*, Seoul, South Korea, 2016, pp. 570-582.

doi:10.1109/ISCA.2016.56

CITATIONS

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