The Community for Technology Leaders
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA) (2014)
Minneapolis, MN, USA
June 14, 2014 to June 18, 2014
ISBN: 978-1-4799-4396-8
TABLE OF CONTENTS

Author index (PDF)

pp. 553-554

[Front cover] (PDF)

pp. c1

Table of contents (PDF)

pp. vii-xi

A low power and reliable charge pump design for Phase Change Memories (Abstract)

Lei Jiang , Electrical and Computer Engineering Department, University of Pittsburgh, USA
Bo Zhao , Electrical and Computer Engineering Department, University of Pittsburgh, USA
Jun Yang , Electrical and Computer Engineering Department, University of Pittsburgh, USA
Youtao Zhang , Computer Science Department, University of Pittsburgh, USA
pp. 397-408

A reconfigurable fabric for accelerating large-scale datacenter services (Abstract)

Andrew Putnam , Microsoft, USA
Adrian M. Caulfield , Microsoft, USA
Eric S. Chung , Microsoft, USA
Derek Chiou , Microsoft and University of Texas at Austin, USA
Kypros Constantinides , Amazon Web Services, USA
John Demme , Columbia University, USA
Hadi Esmaeilzadeh , Georgia Institute of Technology, USA
Jeremy Fowers , Microsoft, USA
Gopi Prashanth Gopal , Microsoft, USA
Jan Gray , Microsoft, USA
Michael Haselman , Microsoft, USA
Scott Hauck , Microsoft and University of Washington, USA
Stephen Heil , Microsoft, USA
Amir Hormati , Google, Inc., USA
Joo-Young Kim , Microsoft, USA
Sitaram Lanka , Microsoft, USA
James Larus , École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Eric Peterson , Microsoft, USA
Simon Pope , Microsoft, USA
Aaron Smith , Microsoft, USA
Jason Thong , Microsoft, USA
Phillip Yi Xiao , Microsoft, USA
Doug Burger , Microsoft, USA
pp. 13-24

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures (Abstract)

Yakun Sophia Shao , Harvard University, USA
Brandon Reagen , Harvard University, USA
Gu-Yeon Wei , Harvard University, USA
David Brooks , Harvard University, USA
pp. 97-108

An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs (Abstract)

Karthik Swaminathan , The Pennsylvania State University, USA
Huichu Liu , The Pennsylvania State University, USA
Jack Sampson , The Pennsylvania State University, USA
Vijaykrishnan Narayanan , The Pennsylvania State University, USA
pp. 241-252

ArchRanker: A ranking approach to design space exploration (Abstract)

Tianshi Chen , State Key Laboratory of Computer Architecture, Institute of Computing Technology (ICT), CAS, China
Qi Guo , Carnegie Mellon University, United States
Ke Tang , University of Science and Technology of China, China
Olivier Temam , Inria, France
Zhiwei Xu , State Key Laboratory of Computer Architecture, Institute of Computing Technology (ICT), CAS, China
Zhi-Hua Zhou , National Key Laboratory for Novel Software Technology, Nanjing University, China
Yunji Chen , State Key Laboratory of Computer Architecture, Institute of Computing Technology (ICT), CAS, China
pp. 85-96

Architecture implications of pads as a scarce resource (Abstract)

Runjie Zhang , University of Virginia, USA
Ke Wang , University of Virginia, USA
Brett H. Meyer , McGill University, USA
Mircea R. Stan , University of Virginia, USA
Kevin Skadron , University of Virginia, USA
pp. 373-384

Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery (Abstract)

Gaurang Upasani , Dept. d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain
Xavier Vera , Intel Barcelona Research Center, Intel Labs, Spain
Antonio Gonzalez , Dept. d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain
pp. 37-48

The CHERI capability model: Revisiting RISC in an age of risk (Abstract)

Jonathan Woodruff , University of Cambridge, UK
Robert N. M. Watson , University of Cambridge, UK
David Chisnall , University of Cambridge, UK
Simon W. Moore , University of Cambridge, UK
Jonathan Anderson , University of Cambridge, UK
Brooks Davis , SRI International, UK
Ben Laurie , Google UK Ltd, UU
Peter G. Neumann , SRI International, UK
Robert Norton , University of Cambridge, UK
Michael Roe , University of Cambridge, UK
pp. 457-468

CODOMs: Protecting software with Code-centric memory Domains (Abstract)

Lluis Vilanova , Barcelona Supercomputing Center (BSC) & Universitat Politècnica de Catalunya (UPC), Spain
Muli Ben-Yehuda , Computer Science, Technion- Israel Institute of Technology, Haifa, Israel
Nacho Navarro , Barcelona Supercomputing Center (BSC) & Universitat Politècnica de Catalunya (UPC), Spain
Yoav Etsion , Electrical Engineering, Technion- Israel Institute of Technology, Haifa, Israel
Mateo Valero , Barcelona Supercomputing Center (BSC) & Universitat Politècnica de Catalunya (UPC), Spain
pp. 469-480

Navigating the cache hierarchy with a single lookup (Abstract)

Andreas Sembrant , Uppsala University, Department of Information Technology, P.O. Box 337, SE-751 05, Sweden
Erik Hagersten , Uppsala University, Department of Information Technology, P.O. Box 337, SE-751 05, Sweden
David Black-Schaffer , Uppsala University, Department of Information Technology, P.O. Box 337, SE-751 05, Sweden
pp. 133-144

The Dirty-Block Index (Abstract)

Vivek Seshadri , Carnegie Mellon University, USA
Abhishek Bhowmick , Carnegie Mellon University, USA
Onur Mutlu , Carnegie Mellon University, USA
Phillip B. Gibbons , Intel Pittsburgh, USA
Michael A. Kozuch , Intel Pittsburgh, USA
Todd C. Mowry , Carnegie Mellon University, USA
pp. 157-168

EOLE: Paving the way for an effective implementation of value prediction (Abstract)

Arthur Perais , IRISA/INRIA, France
Andre Seznec , IRISA/INRIA, France
pp. 481-492

Efficient digital neurons for large scale cortical architectures (Abstract)

James E. Smith , University of Wisconsin-Madison, USA
pp. 229-240

Eliminating redundant fragment shader executions on a mobile GPU via hardware memoization (Abstract)

Jose-Maria Arnau , Universitat Politecnica de Catalunya, Spain
Joan-Manuel Parcerisa , Universitat Politecnica de Catalunya, Spain
Polychronis Xekalakis , Intel Corporation, USA
pp. 529-540

Enabling preemptive multiprogramming on GPUs (Abstract)

Ivan Tanasic , Barcelona Supercomputing Center, Spain
Isaac Gelado , NVIDIA Research, USA
Javier Cabezas , Barcelona Supercomputing Center, Spain
Alex Ramirez , Barcelona Supercomputing Center, Spain
Nacho Navarro , Barcelona Supercomputing Center, Spain
Mateo Valero , Barcelona Supercomputing Center, Spain
pp. 193-204

Fine-grain task aggregation and coordination on GPUs (Abstract)

Marc S. Orr , University of Wisconsin-Madison, Computer Sciences, USA
Bradford M. Beckmann , AMD Research, USA
Steven K. Reinhardt , AMD Research, USA
David A. Wood , University of Wisconsin-Madison, Computer Sciences, USA
pp. 181-192

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors (Abstract)

Yoongu Kim , Carnegie Mellon University, USA
Ross Daly , Carnegie Mellon University, USA
Jeremie Kim , Carnegie Mellon University, USA
Chris Fallin , Carnegie Mellon University, USA
Ji Hye Lee , Carnegie Mellon University, USA
Donghyuk Lee , Carnegie Mellon University, USA
Chris Wilkerson , Intel Labs, USA
Konrad Lai , Carnegie Mellon University, USA
Onur Mutlu , Carnegie Mellon University, USA
pp. 361-372

Fractal++: Closing the performance gap between fractal and conventional coherence (Abstract)

Gwendolyn Voskuilen , School of Electrical and Computer Engineering, Purdue University, USA
T. N. Vijaykumar , School of Electrical and Computer Engineering, Purdue University, USA
pp. 409-420

GangES: Gang error simulation for hardware resiliency evaluation (Abstract)

Radha Venkatagiri , University of Illinois at Urbana-Champaign, USA
Sarita V. Adve , University of Illinois at Urbana-Champaign, USA
Helia Naeimi , Intel Labs, USA
pp. 61-72

General-purpose code acceleration with limited-precision analog computation (Abstract)

Renee St. Amant , University of Texas at Austin, USA
Amir Yazdanbakhsh , Georgia Institute of Technology, USA
Jongse Park , Georgia Institute of Technology, USA
Bradley Thwaites , Georgia Institute of Technology, USA
Hadi Esmaeilzadeh , Georgia Institute of Technology, USA
Arjang Hassibi , University of Texas at Austin, USA
Luis Ceze , University of Washington, USA
Doug Burger , Microsoft Research, USA
pp. 505-516

Going vertical in memory management: Handling multiplicity by multi-policy (Abstract)

Lei Liu , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
Yong Li , Department of ECE, University of Pittsburgh, USA
Zehan Cui , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
Yungang Bao , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
Mingyu Chen , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
Chengyong Wu , State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China
pp. 169-180

HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs (Abstract)

Simone Campanoni , Harvard University, Cambridge, MA, USA
Kevin Brownell , Harvard University, Cambridge, MA, USA
Svilen Kanev , Harvard University, Cambridge, MA, USA
Timothy M. Jones , University of Cambridge, UK
Gu-Yeon Wei , Harvard University, Cambridge, MA, USA
David Brooks , Harvard University, Cambridge, MA, USA
pp. 217-228

HIOS: A host interface I/O scheduler for Solid State Disks (Abstract)

Myoungsoo Jung , Department of EE, The University of Texas at Dallas, USA
Wonil Choi , Department of EE, The University of Texas at Dallas, USA
Shekhar Srikantaiah , Qualcomm, Daegu University, Korea
Joonhyuk Yoo , College of ICE, Daegu University, Korea
Mahmut T. Kandemir , Department of CSE, The Pennsylvania State University, USA
pp. 289-300

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation (Abstract)

Tao Zhang , Pennsylvania State University, USA
Ke Chen , Oracle Corporation, USA
Cong Xu , Pennsylvania State University, USA
Guangyu Sun , Peking University, China
Tao Wang , Peking University, China
Yuan Xie , Pennsylvania State University, USA
pp. 349-360

Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor (Abstract)

Ashish Venkat , University of California, San Diego, USA
Dean M. Tullsen , University of California, San Diego, USA
pp. 121-132

Improving the energy efficiency of Big Cores (Abstract)

Kenneth Czechowski , Georgia Institute of Technology, Atlanta, USA
Victor W. Lee , Intel Corporation, Santa Clara, CA, USA
Ed Grochowski , Intel Corporation, Santa Clara, CA, USA
Ronny Ronen , Intel Corporation, Santa Clara, CA, USA
Ronak Singhal , Intel Corporation, Santa Clara, CA, USA
Richard Vuduc , Georgia Institute of Technology, Atlanta, USA
Pradeep Dubey , Intel Corporation, Santa Clara, CA, USA
pp. 493-504

Increasing off-chip bandwidth in multi-core processors with switchable pins (Abstract)

Shaoming Chen , Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, USA
Yue Hu , Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, USA
Ying Zhang , Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, USA
Lu Peng , Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, USA
Jesse Ardonne , Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, USA
Samuel Irving , Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, USA
Ashok Srivastava , Division of Electrical & Computer Engineering, School of Electrical Engineering and Computer Science, Louisiana State University, USA
pp. 385-396

MemGuard: A low cost and energy efficient design to support and enhance memory system reliability (Abstract)

Long Chen , Department of Electrical and Computer Engineering, Iowa State University, US
Zhao Zhang , Department of Electrical and Computer Engineering, Iowa State University, US
pp. 49-60

Memory persistency (Abstract)

Steven Pelley , University of Michigan, USA
Peter M. Chen , University of Michigan, USA
Thomas F. Wenisch , University of Michigan, USA
pp. 265-276

OmniOrder: Directory-based conflict serialization of transactions (Abstract)

Xuehai Qian , University of California, Berkeley, USA
Benjamin Sahelices , Universidad de Valladolid, Spain
Josep Torrellas , University of Illinois, Urbana-Champaign, USA
pp. 421-432

Optimizing virtual machine consolidation performance on NUMA server architecture for cloud workloads (Abstract)

Ming Liu , Intelligent Design of Efficient Architectures Laboratory (IDEAL), Department of Electrical and Computer Engineering, University of Florida, USA
Tao Li , Intelligent Design of Efficient Architectures Laboratory (IDEAL), Department of Electrical and Computer Engineering, University of Florida, USA
pp. 325-336

Pacifier: Record and replay for relaxed-consistency multiprocessors with distributed directory protocol (Abstract)

Xuehai Qian , University of California Berkeley, USA
Benjamin Sahelices , Universidad de Valladolid, Spain
Depei Qian , Beihang University, China
pp. 433-444

Race Logic: A hardware acceleration for dynamic programming algorithms (Abstract)

Advait Madhavan , University of California, Santa Barbara, USA
Timothy Sherwood , University of California, Santa Barbara, USA
Dmitri Strukov , University of California, Santa Barbara, USA
pp. 517-528

Real-world design and evaluation of compiler-managed GPU redundant multithreading (Abstract)

Jack Wadden , University of Virginia, Charlottesville, USA
Alexander Lyashevsky , AMD Research, Advanced Micro Devices, Inc., Sunnyvale, CA, USA
Sudhanva Gurumurthi , AMD Research, Advanced Micro Devices, Inc., Boxborough, MA, USA
Vilas Sridharan , RAS Architecture, Advanced Micro Devices, Inc., Boxborough, MA, USA
Kevin Skadron , University of Virginia, Charlottesville, USA
pp. 73-84

Reducing access latency of MLC PCMs through line striping (Abstract)

Morteza Hoseinzadeh , HPCAN Lab, Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
Mohammad Arjomand , HPCAN Lab, Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
Hamid Sarbazi-Azad , HPCAN Lab, Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
pp. 277-288

Replay debugging: Leveraging record and replay for program debugging (Abstract)

Nima Honarmand , University of Illinois at Urbana-Champaign, USA
Josep Torrellas , University of Illinois at Urbana-Champaign, USA
pp. 455-456

Row-buffer decoupling: A case for low-latency DRAM microarchitecture (Abstract)

Seongil O , Seoul National University, Korea
Young Hoon Son , Seoul National University, Korea
Nam Sung Kim , University of Wisconsin-Madison, USA
Jung Ho Ahn , Seoul National University, Korea
pp. 337-348

SC2: A statistical compression cache scheme (Abstract)

Angelos Arelakis , Chalmers University of Technology, Gothenburg, Sweden
Per Stenstrom , Chalmers University of Technology, Gothenburg, Sweden
pp. 145-156

SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering (Abstract)

Bhavya K. Daya , Massachusetts Institute of Technology, USA
Chia-Hsin Owen Chen , Massachusetts Institute of Technology, USA
Suvinay Subramanian , Massachusetts Institute of Technology, USA
Woo-Cheol Kwon , Massachusetts Institute of Technology, USA
Sunghyun Park , Massachusetts Institute of Technology, USA
Tushar Krishna , Massachusetts Institute of Technology, USA
Jim Holt , Massachusetts Institute of Technology, USA
Anantha P. Chandrakasan , Massachusetts Institute of Technology, USA
Li-Shiuan Peh , Massachusetts Institute of Technology, USA
pp. 25-36

STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies (Abstract)

Rangharajan Venkatesan , School of Electrical and Computer Engineering, Purdue University, USA
Shankar Ganesh Ramasubramanian , School of Electrical and Computer Engineering, Purdue University, USA
Swagath Venkataramani , School of Electrical and Computer Engineering, Purdue University, USA
Kaushik Roy , School of Electrical and Computer Engineering, Purdue University, USA
Anand Raghunathan , School of Electrical and Computer Engineering, Purdue University, USA
pp. 253-264

Single-graph multiple flows: Energy efficient design alternative for GPGPUs (Abstract)

Dani Voitsechov , Electrical Engineering, Technion - Israel Institute of Technology, Israel
Yoav Etsion , Electrical Engineering, Technion - Israel Institute of Technology, Israel
pp. 205-216

SleepScale: Runtime joint speed scaling and sleep states management for power efficient data centers (Abstract)

Yanpei Liu , University of Wisconsin Madison, USA
Stark C. Draper , University of Toronto, Canada
Nam Sung Kim , University of Wisconsin Madison, USA
pp. 313-324

SynFull: Synthetic traffic models capturing cache coherent behaviour (Abstract)

Mario Badr , Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Canada
Natalie Enright Jerger , Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Canada
pp. 109-120

Towards energy proportionality for large-scale latency-critical workloads (Abstract)

David Lo , Stanford University, USA
Liqun Cheng , Google, Inc., USA
Rama Govindaraju , Google, Inc., USA
Luiz Andre Barroso , Google, Inc., USA
Christos Kozyrakis , Stanford University, USA
pp. 301-312

Unifying on-chip and inter-node switching within the Anton 2 network (Abstract)

Brian Towles , D. E. Shaw Research, New York, 10036, USA
J.P. Grossman , D. E. Shaw Research, New York, 10036, USA
Brian Greskamp , D. E. Shaw Research, New York, 10036, USA
David E. Shaw , D. E. Shaw Research, New York, 10036, USA
pp. 1-12

WebCore: Architectural support for mobile Web browsing (Abstract)

Yuhao Zhu , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
Vijay Janapa Reddi , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
pp. 541-552
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