The Community for Technology Leaders
Computer Architecture, International Symposium on (2012)
Portland, OR USA
June 9, 2012 to June 13, 2012
ISSN: 1063-6897
ISBN: 978-1-4673-0475-7
TABLE OF CONTENTS

RAIDR: Retention-aware intelligent DRAM refresh (PDF)

Jamie Liu , Carnegie Mellon University, USA
Ben Jaiyen , Carnegie Mellon University, USA
Richard Veras , Carnegie Mellon University, USA
Onur Mutlu , Carnegie Mellon University, USA
pp. 1-12

PARDIS: A programmable memory controller for the DDRx interfacing standards (PDF)

Mahdi Nazm Bojnordi , University of Rochester, NY 14627 USA
Engin Ipek , University of Rochester, NY 14627 USA
pp. 13-24

BOOM: Enabling mobile memory based low-power server DIMMs (PDF)

Doe Hyun Yoon , Intelligent Infrastructure Lab, Hewlett-Packard Labs, USA
Jichuan Chang , Intelligent Infrastructure Lab, Hewlett-Packard Labs, USA
Naveen Muralimanohar , Intelligent Infrastructure Lab, Hewlett-Packard Labs, USA
Parthasarathy Ranganathan , Intelligent Infrastructure Lab, Hewlett-Packard Labs, USA
pp. 25-36

Towards energy-proportional datacenter memory with mobile DRAM (PDF)

Krishna T. Malladi , Electrical Engineering, Stanford University, USA
Frank A. Nothaft , Electrical Engineering, Stanford University, USA
Karthika Periyathambi , Electrical Engineering, Stanford University, USA
Benjamin C. Lee , Electrical and Computer Engineering, Duke University, USA
Christos Kozyrakis , Electrical Engineering, Stanford University, USA
Mark Horowitz , Electrical Engineering, Stanford University, USA
pp. 37-48

Simultaneous branch and warp interweaving for sustained GPU performance (PDF)

Nicolas Brunie , Kalray and ENS de Lyon, USA
Sylvain Collange , Universidade Federal de Minas Gerais, Brazil
Gregory Diamos , NVIDIA Research, USA
pp. 49-60

CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures (PDF)

Minsoo Rhu , Electrical and Computer Engineering Department, The University of Texas at Austin, USA
Mattan Erez , Electrical and Computer Engineering Department, The University of Texas at Austin, USA
pp. 61-71

iGPU: Exception support and speculative execution on GPUs (PDF)

Jaikrishnan Menon , Department of Computer Sciences, University of Wisconsin-Madison, USA
Marc de Kruijf , Department of Computer Sciences, University of Wisconsin-Madison, USA
Karthikeyan Sankaralingam , Department of Computer Sciences, University of Wisconsin-Madison, USA
pp. 72-83

Boosting mobile GPU performance with a decoupled access/execute fragment processor (PDF)

Jose-Maria Arnau , Computer Architecture Department, Universitat Politècnica de Catalunya, Spain
Joan-Manuel Parcerisa , Computer Architecture Department, Universitat Politècnica de Catalunya, Spain
Polychronis Xekalakis , Intel Barcelona Research Center, Intel Labs Barcelona, Spain
pp. 84-93

Branch regulation: Low-overhead protection from code reuse attacks (PDF)

Mehmet Kayaalp , Department of Computer Science, State University of New York at Binghamton, USA
Meltem Ozsoy , Department of Computer Science, State University of New York at Binghamton, USA
Nael Abu-Ghazaleh , Department of Computer Science, State University of New York at Binghamton, USA
Dmitry Ponomarev , Department of Computer Science, State University of New York at Binghamton, USA
pp. 94-105

Side-channel vulnerability factor: A metric for measuring information leakage (PDF)

John Demme , Computer Architecture Security and Technology Lab, Department of Computer Science, Columbia University, NY, 10027, USA
Robert Martin , Computer Architecture Security and Technology Lab, Department of Computer Science, Columbia University, NY, 10027, USA
Adam Waksman , Computer Architecture Security and Technology Lab, Department of Computer Science, Columbia University, NY, 10027, USA
Simha Sethumadhavan , Computer Architecture Security and Technology Lab, Department of Computer Science, Columbia University, NY, 10027, USA
pp. 106-117

TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks (PDF)

Robert Martin , 4Computer Architecture and Security Technologies Lab, Department of Computer Science, Columbia University, New York, USA
John Demme , 4Computer Architecture and Security Technologies Lab, Department of Computer Science, Columbia University, New York, USA
Simha Sethumadhavan , 4Computer Architecture and Security Technologies Lab, Department of Computer Science, Columbia University, New York, USA
pp. 118-129

Inspection resistant memory: Architectural support for security from physical examination (PDF)

Jonathan Valamehr , UC Santa Barbara, USA
Melissa Chase , Microsoft Research, USA
Seny Kamara , Microsoft Research, USA
Andrew Putnam , Microsoft Research, USA
Dan Shumow , Microsoft Research, USA
Vinod Vaikuntanathan , University of Toronto, Canada
Timothy Sherwood , UC Santa Barbara, USA
pp. 130-141

Tolerating process variations in nanophotonic on-chip networks (PDF)

Yi Xu , Department of Electrical and Computer Engineering, University of Pittsburgh, USA
Jun Yang , Department of Electrical and Computer Engineering, University of Pittsburgh, USA
Rami Melhem , Department of Computer Science, University of Pittsburgh, USA
pp. 142-152

A micro-architectural analysis of switched photonic multi-chip interconnects (PDF)

Pranay Koka , Oracle Labs, USA
Michael O. McCracken , Oracle Labs, USA
Herb Schwetman , Oracle Labs, USA
Chia-Hsin Owen Chen , MIT CSAIL, USA
Xuezhe Zheng , Oracle Labs, USA
Ron Ho , Oracle Labs, USA
Kannan Raj , Oracle Labs, USA
Ashok V. Krishnamoorthy , Oracle Labs, USA
pp. 153-164

Enhancing effective throughput for transmission line-based bus (PDF)

Aaron Carpenter , Binghamton University, USA
Jianyun Hu , Dept. of Electrical and Computer Engineering, University of Rochester, USA
Ovunc Kocabas , Dept. of Electrical and Computer Engineering, University of Rochester, USA
Michael Huang , Dept. of Electrical and Computer Engineering, University of Rochester, USA
Hui Wu , Dept. of Electrical and Computer Engineering, University of Rochester, USA
pp. 165-176

A case for random shortcut topologies for HPC interconnects (PDF)

Michihiro Koibuchi , National Institute of Informatics / SOKENDAI, 2-1-2, Hitotsubashi, Chiyoda-ku, Tokyo, JAPAN 101-8430
Hiroki Matsutani , Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama, JAPAN 223-8522
Hideharu Amano , Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama, JAPAN 223-8522
D. Frank Hsu , Fordham University, 113 West 60th Street, New York, 10023, USA
Henri Casanova , University of Hawai'i at Manoa, 1680 East-West Road, Honolulu, 96822, USA
pp. 177-188

Watchdog: Hardware for safe and secure manual memory management and full memory safety (PDF)

Santosh Nagarakatte , Computer and Information Science, University of Pennsylvania, USA
Milo M. K. Martin , Computer and Information Science, University of Pennsylvania, USA
Steve Zdancewic , Computer and Information Science, University of Pennsylvania, USA
pp. 189-200

RADISH: Always-on sound and complete race detection in software and hardware (PDF)

Joseph Devietti , University of Washington, USA
Benjamin P. Wood , University of Washington, USA
Karin Strauss , University of Washington, USA
Luis Ceze , University of Washington, USA
Dan Grossman , University of Washington, USA
Shaz Qadeer , Microsoft Research, USA
pp. 201-212

Scheduling heterogeneous multi-cores through performance impact estimation (PIE) (PDF)

Kenzo Van Craeynest , Ghent University, Belgium
Aamer Jaleel , Intel Corporation, VSSAD, Hudson, MA, USA
Lieven Eeckhout , Ghent University, Belgium
Paolo Narvaez , Intel Corporation, VSSAD, Hudson, MA, USA
Joel Emer , Intel Corporation, VSSAD, Hudson, MA, USA
pp. 213-224

The Yin and Yang of power and performance for asymmetric hardware and managed software (PDF)

Ting Cao , Australian National University, Australia
Stephen M Blackburn , Australian National University, Australia
Tiejun Gao , Australian National University, Australia
Kathryn S McKinley , Microsoft Research, USA
pp. 225-236

Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures (PDF)

Evgeni Krimer , Electrical and Computer Engineering Department, The University of Texas at Austin, USA
Patrick Chiang , School of Electrical Engineering and Computer Science, Oregon State University, USA
Mattan Erez , Electrical and Computer Engineering Department, The University of Texas at Austin, USA
pp. 237-248

VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors (PDF)

Timothy N. Miller , Department of Computer Science and Engineering, The Ohio State University, USA
Renji Thomas , Department of Computer Science and Engineering, The Ohio State University, USA
Xiang Pan , Department of Computer Science and Engineering, The Ohio State University, USA
Radu Teodorescu , Department of Computer Science and Engineering, The Ohio State University, USA
pp. 249-260

A first-order mechanistic model for architectural vulnerability factor (PDF)

Arun Arvind Nair , The University of Texas at Austin, USA
Stijn Eyerman , Ghent University, Belgium
Lieven Eeckhout , Ghent University, Belgium
Lizy Kurian John , The University of Texas at Austin, USA
pp. 273-284

LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems (PDF)

Aniruddha N. Udipi , University of Utah, USA
Naveen Muralimanohar , HP Labs, USA
Rajeev Balsubramonian , University of Utah, USA
Al Davis , University of Utah, USA
Norman P. Jouppi , HP Labs, USA
pp. 285-296

Reducing memory reference energy with opportunistic virtual caching (PDF)

Arkaprava Basu , University of Wisconsin-Madison, USA
Mark D. Hill , University of Wisconsin-Madison, USA
Michael M. Swift , University of Wisconsin-Madison, USA
pp. 297-308

Improving writeback efficiency with decoupled last-write prediction (PDF)

Zhe Wang , The University of Texas at San Antonio, USA
Samira M. Khan , The University of Texas at San Antonio, USA
Daniel A. Jimenez , The University of Texas at San Antonio, USA
pp. 309-320

FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion (PDF)

Jaewoong Sim , Georgia Institute of Technology, USA
Jaekyu Lee , Georgia Institute of Technology, USA
Moinuddin K. Qureshi , Georgia Institute of Technology, USA
Hyesoon Kim , Georgia Institute of Technology, USA
pp. 321-332

Setting an error detection infrastructure with low cost acoustic wave detectors (PDF)

Gaurang Upasani , Dept. d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain
Xavier Vera , Intel Barcelona Research Center, Intel Labs, Barcelona, Spain
Antonio Gonzalez , Dept. d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain
pp. 333-343

Viper: Virtual pipelines for enhanced reliability (PDF)

Andrea Pellegrini , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA
Joseph L. Greathouse , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA
Valeria Bertacco , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, USA
pp. 344-355

A case for exploiting subarray-level parallelism (SALP) in DRAM (PDF)

Yoongu Kim , Carnegie Mellon University, USA
Vivek Seshadri , Carnegie Mellon University, USA
Donghyuk Lee , Carnegie Mellon University, USA
Jamie Liu , Carnegie Mellon University, USA
Onur Mutlu , Carnegie Mellon University, USA
pp. 368-379

PreSET: Improving performance of phase change memories by exploiting asymmetry in write times (PDF)

Moinuddin K. Qureshi , Georgia Institute of Technology, USA
Michele M. Franceschini , IBM T. J. Watson Research Center, NY, USAs
Ashish Jagmohan , IBM T. J. Watson Research Center, NY, USAs
Luis A. Lastras , IBM T. J. Watson Research Center, NY, USAs
pp. 380-391

Buffer-on-board memory systems (PDF)

Elliott Cooper-Balis , University of Maryland, USA
Paul Rosenfeld , University of Maryland, USA
Bruce Jacob , University of Maryland, USA
pp. 392-403

Physically addressed queueing (PAQ): Improving parallelism in solid state disks (PDF)

Myoungsoo Jung , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Ellis H. Wilson , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Mahmut Kandemir , Department of Computer Science and Engineering, The Pennsylvania State University, USA
pp. 404-415

Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems (PDF)

Rachata Ausavarungnirun , Carnegie Mellon University, USA
Kevin Kai-Wei Chang , Carnegie Mellon University, USA
Lavanya Subramanian , Carnegie Mellon University, USA
Gabriel H. Loh , Advanced Micro Devices, Inc., USA
Onur Mutlu , Carnegie Mellon University, USA
pp. 416-427

Probabilistic Shared Cache Management (PriSM) (PDF)

R Manikantan , Department of Computer Science and Automation, Indian Institute of Science, Bangalore, India
Kaushik Rajan , Microsoft Research India, Bangalore, India
R Govindarajan , Department of Computer Science and Automation, Indian Institute of Science, Bangalore, India
pp. 428-439

Can traditional programming bridge the Ninja performance gap for parallel computing applications? (PDF)

Nadathur Satish , Parallel Computing Lab, Intel Corporation, USA
Changkyu Kim , Parallel Computing Lab, Intel Corporation, USA
Jatin Chhugani , Parallel Computing Lab, Intel Corporation, USA
Hideki Saito , Intel Compiler Lab, Intel Corporation, USA
Rakesh Krishnaiyer , Intel Compiler Lab, Intel Corporation, USA
Mikhail Smelyanskiy , Parallel Computing Lab, Intel Corporation, USA
Milind Girkar , Intel Compiler Lab, Intel Corporation, USA
Pradeep Dubey , Parallel Computing Lab, Intel Corporation, USA
pp. 440-451

Harmony: Collection and analysis of parallel block vectors (PDF)

Melanie Kambadur , Columbia University, New York, USA
Kui Tang , Columbia University, New York, USA
Martha A. Kim , Columbia University, New York, USA
pp. 452-463

Configurable fine-grain protection for multicore processor virtualization (PDF)

David Wentzlaff , Princeton University, USA
Christopher J. Jackson , Tilera Corp., USA
Patrick Griffin , Google Inc., USA
Anant Agarwal , Tilera Corp., USA
pp. 464-475

Revisiting hardware-assisted page walks for virtualized systems (PDF)

Jeongseob Ahn , Computer Science Department, KAIST, Korea
Seongwook Jin , Computer Science Department, KAIST, Korea
Jaehyuk Huh , Computer Science Department, KAIST, Korea
pp. 476-487

Managing distributed UPS energy for effective power capping in data centers (PDF)

Vasileios Kontorinis , Department of Computer Science and Engineering, UC San Diego, USA
Liuyi Eric Zhang , Department of Computer Science and Engineering, UC San Diego, USA
Baris Aksanli , Department of Computer Science and Engineering, UC San Diego, USA
Jack Sampson , Department of Computer Science and Engineering, UC San Diego, USA
Houman Homayoun , Department of Computer Science and Engineering, UC San Diego, USA
Eddie Pettis , Google Inc., USA
Dean M. Tullsen , Department of Computer Science and Engineering, UC San Diego, USA
Tajana Simunic Rosing , Department of Computer Science and Engineering, UC San Diego, USA
pp. 488-499

Scale-out processors (PDF)

Pejman Lotfi-Kamran , EcoCloud, EPFL, Switzerland
Boris Grot , EcoCloud, EPFL, Switzerland
Michael Ferdman , CALCM, Carnegie Mellon, USA
Stavros Volos , EcoCloud, EPFL, Switzerland
Onur Kocberber , EcoCloud, EPFL, Switzerland
Javier Picorel , EcoCloud, EPFL, Switzerland
Almutaz Adileh , EcoCloud, EPFL, Switzerland
Djordje Jevdjic , EcoCloud, EPFL, Switzerland
Sachin Idgunji , ARM, UK
Emre Ozer , ARM, UK
Babak Falsafi , EcoCloud, EPFL, Switzerland
pp. 500-511

iSwitch: Coordinating and optimizing renewable energy powered server clusters (PDF)

Chao Li , Intelligent Design of Efficient Architectures Laboratory (IDEAL), Department of Electrical and Computer Engineering, University of Florida, USA
Amer Qouneh , Intelligent Design of Efficient Architectures Laboratory (IDEAL), Department of Electrical and Computer Engineering, University of Florida, USA
Tao Li , Intelligent Design of Efficient Architectures Laboratory (IDEAL), Department of Electrical and Computer Engineering, University of Florida, USA
pp. 512-523

End-to-end sequential consistency (PDF)

Abhayendra Singh , University of Michigan, Ann Arbor, USA
Satish Narayanasamy , University of Michigan, Ann Arbor, USA
Daniel Marino , Symantec, USA
Todd Millstein , University of California, Los Angeles, USA
Madanlal Musuvathi , Microsoft Research, Redmond, USA
pp. 524-535

BlockChop: Dynamic squash elimination for hybrid processor architecture (PDF)

Jason Mars , University of Virginia, USA
Naveen Kumar , Intel Corporation, USA
pp. 536-547

The dynamic granularity memory system (PDF)

Doe Hyun Yoon , Intelligent Infrastructure Lab, Hewlett-Packard Labs, USA
Min Kyu Jeong , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
Michael Sullivan , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
Mattan Erez , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
pp. 548-560
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