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2011 ACM/IEEE 38th International Symposium on Computer Architecture (ISCA) (2011)
San Jose, CA
June 4, 2011 to June 8, 2011
ISSN: 1063-6897
ISBN: 978-1-4503-0472-6
TABLE OF CONTENTS

Automatic abstraction and fault tolerance in cortical microachitectures (Abstract)

A. Hashmi , Univ. of Wisconsin, Madison, WI, USA
H. Berry , INRIA Rhone-Alpes, Villeurbanne, France
O. Temam , INRIA Saclay, Orsay, France
M. Lipasti , Univ. of Wisconsin, Madison, WI, USA
pp. 1-10

FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template (Abstract)

N. K. Choudhary , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
S. V. Wadhavkar , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
T. A. Shah , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
H. Mayukh , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
J. Gandhi , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
B. H. Dwiel , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
S. Navada , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
H. H. Najaf-abadi , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
E. Rotenberg , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 11-22

CRIB: Consolidated rename, issue, and bypass (Abstract)

E. Gunadi , Intel Corp., Santa Clara, CA, USA
M. Lipasti , Dept. of Electr. & Comput. Eng., Univ. of Wisconsin - Madison, Madison, WI, USA
pp. 23-32

FlexBulk: Intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes (PDF)

Rishi Agarwal , University of Illinois at Urbana-Champaign, USA
Josep Torrellas , University of Illinois at Urbana-Champaign, USA
pp. 33-44

Virtualizing performance asymmetric multi-core systems (PDF)

Youngjin Kwon , Computer Science Department, KAIST, Korea
Changdae Kim , Computer Science Department, KAIST, Korea
Seungryoul Maeng , Computer Science Department, KAIST, Korea
Jaehyuk Huh , Computer Science Department, KAIST, Korea
pp. 45-56

Vantage: Scalable and efficient fine-grain cache partitioning (PDF)

Daniel Sanchez , Electrical Engineering Department, Stanford University, USA
Christos Kozyrakis , Electrical Engineering Department, Stanford University, USA
pp. 57-68

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs (PDF)

Asit K. Mishra , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Xiangyu Dong , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Guangyu Sun , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Yuan Xie , Department of Computer Science and Engineering, The Pennsylvania State University, USA
N. Vijaykrishnan , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Chita R. Das , Department of Computer Science and Engineering, The Pennsylvania State University, USA
pp. 69-80

Bypass and insertion algorithms for exclusive last-level caches (PDF)

Jayesh Gaur , Intel Architecture Group, Intel Corporation, Bangalore 560103, INDIA
Mainak Chaudhuri , Department of CSE, Indian Institute of Technology, Kanpur 208016, INDIA
Sreenivas Subramoney , Intel Architecture Group, Intel Corporation, Bangalore 560103, INDIA
pp. 81-92

Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks (PDF)

Blas Cuesta , Department of Computer Engineering, Universitat Politècnica de València, Camino de Vera, s/n, 46021, Valencia, Spain
Alberto Ros , Department of Computer Engineering, Universitat Politècnica de València, Camino de Vera, s/n, 46021, Valencia, Spain
Maria E. Gomez , Department of Computer Engineering, Universitat Politècnica de València, Camino de Vera, s/n, 46021, Valencia, Spain
Antonio Robles , Department of Computer Engineering, Universitat Politècnica de València, Camino de Vera, s/n, 46021, Valencia, Spain
Jose Duato , Department of Computer Engineering, Universitat Politècnica de València, Camino de Vera, s/n, 46021, Valencia, Spain
pp. 93-103

TLSync: Support for multiple fast barriers using on-chip transmission lines (PDF)

Jungju Oh , Georgia Institute of Technology, Atlanta, USA
Milos Prvulovic , Georgia Institute of Technology, Atlanta, USA
Alenka Zajic , Georgia Institute of Technology, Atlanta, USA
pp. 105-115

OUTRIDER: Efficient memory latency tolerance with decoupled strands (Abstract)

N. C. Crago , Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
S. J. Patel , Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
pp. 117-128

Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators (PDF)

Yunsup Lee , Department of Electrical Engineering and Computer Science, University of California, Berkeley, USA
Rimas Avizienis , Department of Electrical Engineering and Computer Science, University of California, Berkeley, USA
Alex Bishara , Department of Electrical Engineering and Computer Science, University of California, Berkeley, USA
Richard Xia , Department of Electrical Engineering and Computer Science, University of California, Berkeley, USA
Derek Lockhart , School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA
Christopher Batten , School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA
Krste Asanovic , Department of Electrical Engineering and Computer Science, University of California, Berkeley, USA
pp. 129-140

Prefetch-aware shared-resource management for multi-core systems (Abstract)

E. Ebrahimi , HPS Res. Group, Univ. of Texas at Austin, Austin, TX, USA
Chang Joo Lee , HPS Res. Group, Univ. of Texas at Austin, Austin, TX, USA
O. Mutlu , Carnegie Mellon Univ., Pittsburgh, PA, USA
Y. N. Patt , HPS Res. Group, Univ. of Texas at Austin, Austin, TX, USA
pp. 141-152

Rebound: Scalable checkpointing for coherent shared memory (Abstract)

R. Agarwal , Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
P. Garg , Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
J. Torrellas , Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
pp. 153-164

Demand-driven software race detection using hardware performance counters (Abstract)

J. L. Greathouse , Univ. of Michigan, Ann Arbor, MI, USA
Zhiqiang Ma , Intel Corp., Hillsboro, OR, USA
M. I. Frank , Intel Corp., Hillsboro, OR, USA
R. Peri , Intel Corp., Hillsboro, OR, USA
T. Austin , Univ. of Michigan, Ann Arbor, MI, USA
pp. 165-176

i-NVMM: A secure non-volatile main memory system with incremental encryption (Abstract)

Siddhartha Chhabra , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Y. Solihin , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 177-188

Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security (Abstract)

M. Tiwari , Dept. of Comput. Sci., Univ. of California, Santa Barbara, CA, USA
J. K. Oberg , Dept. of Comput. Sci., Univ. of California, Santa Barbara, CA, USA
X. Li , Dept. of Comput. Sci., Univ. of California, Santa Barbara, CA, USA
J. Valamehr , Dept. of Comput. Sci., Univ. of California, Santa Barbara, CA, USA
T. Levin , Naval Postgrad. Sch., Monterey, CA, USA
B. Hardekopf , Dept. of Comput. Sci., Univ. of California, Santa Barbara, CA, USA
R. Kastner , Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
F. T. Chong , Dept. of Comput. Sci., Univ. of California, Santa Barbara, CA, USA
T. Sherwood , Dept. of Comput. Sci., Univ. of California, Santa Barbara, CA, USA
pp. 189-199

Sampling + DMR: Practical and low-overhead permanent fault detection (Abstract)

S. Nomura , Vertical Res. Group, Univ. of Wisconsin - Madison, Madison, WI, USA
M. D. Sinclair , Vertical Res. Group, Univ. of Wisconsin - Madison, Madison, WI, USA
Chen-Han Ho , Vertical Res. Group, Univ. of Wisconsin - Madison, Madison, WI, USA
V. Govindaraju , Vertical Res. Group, Univ. of Wisconsin - Madison, Madison, WI, USA
M. de Kruijf , Vertical Res. Group, Univ. of Wisconsin - Madison, Madison, WI, USA
K. Sankaralingam , Vertical Res. Group, Univ. of Wisconsin - Madison, Madison, WI, USA
pp. 201-212

Releasing efficient beta cores to market early (Abstract)

S. Sudhakrishnan , Dept. of Comput. Eng., Univ. of California Santa Cruz, Santa Cruz, CA, USA
R. Dicochea , Dept. of Comput. Eng., Univ. of California Santa Cruz, Santa Cruz, CA, USA
J. Renau , Dept. of Comput. Eng., Univ. of California Santa Cruz, Santa Cruz, CA, USA
pp. 213-221

CPPC: Correctable parity protected cache (Abstract)

M. Manoochehri , Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
M. Annavaram , Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
M. Dubois , Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
pp. 223-234

Energy-efficient mechanisms for managing thread context in throughput processors (Abstract)

Mark Gebhart , Univ. of Texas at Austin, Austin, TX, USA
D. R. Johnson , Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
D. Tarjan , NVIDIA, Santa Clara, CA, USA
S. W. Keckler , Univ. of Texas at Austin, Austin, TX, USA
W. J. Dally , NVIDIA, Santa Clara, CA, USA
E. Lindholm , NVIDIA, Santa Clara, CA, USA
K. Skadron , Univ. of Virginia, Charlottesville, VA, USA
pp. 235-246

SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading (PDF)

Wing-kei S. Yu , Cornell University, Ithaca, NY 14853, USA
Ruirui Huang , Cornell University, Ithaca, NY 14853, USA
Sarah Q. Xu , Cornell University, Ithaca, NY 14853, USA
Sung-En Wang , Cornell University, Ithaca, NY 14853, USA
Edwin Kan , Cornell University, Ithaca, NY 14853, USA
G. Edward Suh , Cornell University, Ithaca, NY 14853, USA
pp. 247-258

An abacus turn model for time/space-efficient reconfigurable routing (PDF)

Binzhang Fu , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Yinhe Han , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Jun Ma , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Huawei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
Xiaowei Li , Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China
pp. 259-270

A case for globally shared-medium on-chip interconnect (PDF)

Aaron Carpenter , Dept. of Electrical & Computer Engineering, University of Rochester, New York 14627, USA
Jianyun Hu , Dept. of Electrical & Computer Engineering, University of Rochester, New York 14627, USA
Jie Xu , Dept. of Electrical & Computer Engineering, University of Rochester, New York 14627, USA
Michael Huang , Dept. of Electrical & Computer Engineering, University of Rochester, New York 14627, USA
Hui Wu , Dept. of Electrical & Computer Engineering, University of Rochester, New York 14627, USA
pp. 271-281

The impact of memory subsystem resource sharing on datacenter applications (PDF)

Lingjia Tang , University of Virginia, USA
Jason Mars , University of Virginia, USA
Neil Vachharajani , Pure Storage, USA
Robert Hundt , Google, USA
Mary Lou Soffa , University of Virginia, USA
pp. 283-294

Adaptive granularity memory systems: A tradeoff between storage efficiency and throughput (PDF)

Doe Hyun Yoon , The University of Texas at Austin, Electrical and Computer Engineering Dept., USA
Min Kyu Jeong , The University of Texas at Austin, Electrical and Computer Engineering Dept., USA
Mattan Erez , The University of Texas at Austin, Electrical and Computer Engineering Dept., USA
pp. 295-306

SpecTLB: A mechanism for speculative address translation (PDF)

Thomas W. Barr , Rice University, Houston, TX, USA
Alan L. Cox , Rice University, Houston, TX, USA
Scott Rixner , Rice University, Houston, TX, USA
pp. 307-317

Power management of online data-intensive services (PDF)

David Meisner , The University of Michigan, USA
Christopher M. Sadler , Google, Inc., USA
Luiz Andre Barroso , Google, Inc., USA
Wolf-Dietrich Weber , Google, Inc., USA
Thomas F. Wenisch , The University of Michigan, USA
pp. 319-330

Fighting fire with fire: Modeling the datacenter-scale effects of targeted superlattice thermal management (PDF)

Susmit Biswas , Lawrence Livermore National Laboratory, CA - 94550, USA
Mohit Tiwari , Department of Computer Science, UC Santa Barbara, USA
Timothy Sherwood , Department of Computer Science, UC Santa Barbara, USA
Luke Theogarajan , Department of Electrical and Computer Engineering, UC Santa Barbara, USA
Frederic T. Chong , Department of Computer Science, UC Santa Barbara, USA
pp. 331-340

Benefits and limitations of tapping into stored energy for datacenters (PDF)

Sriram Govindan , Department of Computer Science and Engineering, The Pennsylvania State University, University Park, USA
Anand Sivasubramaniam , Department of Computer Science and Engineering, The Pennsylvania State University, University Park, USA
Bhuvan Urgaonkar , Department of Computer Science and Engineering, The Pennsylvania State University, University Park, USA
pp. 341-351

Rapid identification of architectural bottlenecks via precise event counting (PDF)

John Demme , Computer Architecture and Security Technologies Lab, Department of Computer Science, Columbia University, New York, USA
Simha Sethumadhavan , Computer Architecture and Security Technologies Lab, Department of Computer Science, Columbia University, New York, USA
pp. 353-364

Dark silicon and the end of multicore scaling (PDF)

Hadi Esmaeilzadeh , University of Washington, USA
Emily Blem , University of Wisconsin-Madison, USA
Renee St. Amant , The University of Texas at Austin, USA
Karthikeyan Sankaralingam , University of Wisconsin-Madison, USA
Doug Burger , Microsoft Research, USA
pp. 365-376

Moguls: A model to explore the memory hierarchy for bandwidth improvements (PDF)

Guangyu Sun , Pennsylvania State University, USA
Christopher Hughes , Intel Labs, USA
Changkyu Kim , Intel Labs, USA
Jishen Zhao , Pennsylvania State University, USA
Cong Xu , Pennsylvania State University, USA
Yuan Xie , Pennsylvania State University, USA
Yen-Kuang Chen , Intel Labs, USA
pp. 377-388

A case for heterogeneous on-chip interconnects for CMPs (PDF)

Asit K. Mishra , Department of Computer Science and Engineering, The Pennsylvania State University, USA
N. Vijaykrishnan , Department of Computer Science and Engineering, The Pennsylvania State University, USA
Chita R. Das , Department of Computer Science and Engineering, The Pennsylvania State University, USA
pp. 389-399

Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees (PDF)

Boris Grot , The University of Texas at Austin, USA
Joel Hestness , The University of Texas at Austin, USA
Stephen W. Keckler , The University of Texas at Austin, USA
pp. 401-412

DBAR: An efficient routing algorithm to support multiple concurrent applications in networks-on-chip (PDF)

Sheng Ma , School of Computer, National University of Defense Technology, Changsha, China
Natalie Enright Jerger , Department of Electrical and Computer Engineering, University of Toronto, Canada
Zhiying Wang , School of Computer, National University of Defense Technology, Changsha, China
pp. 413-424

Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems (PDF)

Aniruddha N. Udipi , University of Utah, Salt Lake City, USA
Naveen Muralimanohar , University of Utah, Salt Lake City, USA
Rajeev Balsubramonian , HP Labs, Palo Alto, CA, USA
Al Davis , University of Utah, Salt Lake City, USA
Norman P. Jouppi , HP Labs, Palo Alto, CA, USA
pp. 425-436

The role of optics in future high radix switch design (PDF)

Nathan Binkert , HP Labs, Palo Alto, USA
Al Davis , HP Labs, Palo Alto, USA
Norman P. Jouppi , HP Labs, Palo Alto, USA
Moray McLaren , HP Labs, Palo Alto, USA
Naveen Muralimanohar , HP Labs, Palo Alto, USA
Robert Schreiber , HP Labs, Palo Alto, USA
Jung Ho Ahn , Seoul National University, Korea
pp. 437-447

Scalable power control for many-core architectures running multi-threaded applications (PDF)

Kai Ma , Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, 37996, USA
Xue Li , Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, 37996, USA
Ming Chen , Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, 37996, USA
Xiaorui Wang , Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, 37996, USA
pp. 449-460

Energy-efficient cache design using variable-strength error-correcting codes (PDF)

Alaa R. Alameldeen , Intel Corporation, 2111 NE 25th Ave M/S JF2-04, Hillsboro, OR 97124, USA
Ilya Wagner , Intel Corporation, 2111 NE 25th Ave M/S JF2-04, Hillsboro, OR 97124, USA
Zeshan Chishti , Intel Corporation, 2111 NE 25th Ave M/S JF2-04, Hillsboro, OR 97124, USA
Wei Wu , Intel Corporation, 2111 NE 25th Ave M/S JF2-04, Hillsboro, OR 97124, USA
Chris Wilkerson , Intel Corporation, 2111 NE 25th Ave M/S JF2-04, Hillsboro, OR 97124, USA
Shih-Lien Lu , Intel Corporation, 2111 NE 25th Ave M/S JF2-04, Hillsboro, OR 97124, USA
pp. 461-471
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