The Community for Technology Leaders
Computer Architecture, International Symposium on (2006)
Boston, Massachusetts
June 17, 2006 to June 21, 2006
ISSN: 1063-6897
ISBN: 0-7695-2608-X
TABLE OF CONTENTS
Introduction

list-reviewer (PDF)

pp. xiv
Introduction
Session 1: Interconnection Networks

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks (Abstract)

Dongkook Park , Pennsylvania State University
Jongman Kim , Pennsylvania State University
Chrysostomos Nicopoulos , Pennsylvania State University
pp. 4-15

The BlackWidow High-Radix Clos Network (Abstract)

William J. Dally , Stanford University
Dennis Abts , Cray Inc., Chippewa Falls,Wisconsin
Steve Scott , Cray Inc., Chippewa Falls,Wisconsin
John Kim , Stanford University
pp. 16-28
Session 2: Memory Models

Memory Model = Instruction Reordering + Store Atomicity (Abstract)

Arvind Arvind , MIT CSAIL
Jan-Willem Maessen , Sun Microsystems Laboratories, Burlington, MA
pp. 29-40

Conditional Memory Ordering (Abstract)

Kyung Dong Ryu , IBM T.J. Watson Research Center, Yorktown Heights, NY
Harold W. Cain , IBM T.J. Watson Research Center, Yorktown Heights, NY
Jong-Deok Choi , IBM T.J. Watson Research Center, Yorktown Heights, NY
Christoph von Praun , IBM T.J. Watson Research Center, Yorktown Heights, NY
pp. 41-52

Architectural Semantics for Practical Transactional Memory (Abstract)

Christos Kozyrakis , Stanford University
Chi Cao Minh , Stanford University
Brian D. Carlstrom , Stanford University
Kunle Olukotun , Stanford University
Hassan Chafi , Stanford University
JaeWoong Chung , Stanford University
Austen McDonald , Stanford University
pp. 53-65
Session 3: Power and Thermal Management

Ensemble-level Power Management for Dense Blade Servers (Abstract)

David Irwin , Duke University
Jeffrey Chase , Duke University
Phil Leech , Hewlett Packard
Parthasarathy Ranganathan , Hewlett Packard
pp. 66-77

SODA: A Low-power Architecture For Software Radio (Abstract)

Yuan Lin , University of Michigan at Ann Arbor
Scott Mahlke , University of Michigan at Ann Arbor
Yoav Harel , University of Michigan at Ann Arbor
Trevor Mudge , University of Michigan at Ann Arbor
Krisztian Flautner , ARM, Ltd.n Cambridge,UK
Chaitali Chakrabarti , Arizona State University
Hyunseok Lee , University of Michigan at Ann Arbor
Mark Woh , University of Michigan at Ann Arbor
pp. 89-101
Session 4: Multicore

An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors (Abstract)

Hsien-Hsin S. Lee , Georgia Institute of Technology
Weidong Shi , Georgia Institute of Technology
Laura `Falk , University of Michigan, Ann Arbor
Mrinmoy Ghosh , Georgia Institute of Technology
pp. 102-113

Multiple Instruction Stream Processor (Abstract)

Hong Wang , Microarchitecture Research Lab, Intel Corporation
John P. Shen , Microarchitecture Research Lab, Intel Corporation
Richard A. Hankins , Microarchitecture Research Lab, Intel Corporation
Gautham N. Chinya , Microarchitecture Research Lab, Intel Corporation
Jamison D. Collins , Microarchitecture Research Lab, Intel Corporation
Ryan Rakvic , Microarchitecture Research Lab, Intel Corporation
Perry H. Wang , Microarchitecture Research Lab, Intel Corporation
pp. 114-127
Keynote 2
Session 5A: Memory Access Issues

Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (Abstract)

Chrysostomos Nicopoulos , Pennsylvania State University
Feihui Li , Pennsylvania State University
Yuan Xie , Pennsylvania State University
Thomas Richardson , Pennsylvania State University
Vijaykrishnan Narayanan , Pennsylvania State University
Mahmut Kandemir , Pennsylvania State University
pp. 130-141

Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification (Abstract)

M. Wasiur Rashid , University of Rochester
Alok Garg , University of Rochester
Michael Huang , University of Rochester
pp. 142-154
Session 5B: Cache Design I

Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches (Abstract)

Chuanjun Zhang , University of Missouri-Kansas City
pp. 155-166

A Case for MLP-Aware Cache Replacement (Abstract)

Yale N. Patt , University of Texas at Austin
Onur Mutlu , University of Texas at Austin
Moinuddin K. Qureshi , University of Texas at Austin
Daniel N. Lynch , University of Texas at Austin
pp. 167-178
Session 6A: Security and Network Processors

Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture (Abstract)

Srihari Cadambi , NEC Laboratories America Inc., Princeton, NJ
Srimat Chakradhar , NEC Laboratories America Inc., Princeton, NJ
Jahangir Hasan , Purdue University, West Lafayette, IN
Venkatta Jakkula , NEC Laboratories America Inc., Princeton, NJ
pp. 203-215
Session 6B: Multithreading

Bulk Disambiguation of Speculative Threads in Multiprocessors (Abstract)

Calin Cascaval , IBM T.J. Watson Research Center
James Tuck , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
Luis Ceze , University of Illinois at Urbana-Champaign
pp. 227-238

Learning-Based SMT Processor Resource Distribution via Hill-Climbing (Abstract)

Seungryul Choi , University of Maryland
Donald Yeung , University of Maryland
pp. 239-251
Session 7A: Cache Design II

Spatial Memory Streaming (Abstract)

Andreas Moshovos , University of Toronto
Babak Falsafi , Carnegie Mellon University
Thomas F. Wenisch , Carnegie Mellon University
Anastassia Ailamaki , Carnegie Mellon University
Stephen Somogyi , Carnegie Mellon University
pp. 252-263

Cooperative Caching for Chip Multiprocessors (Abstract)

Jichuan Chang , University of Wisconsin-Madison
Gurindar S. Sohi , University of Wisconsin-Madison
pp. 264-276
Session 7B: Potpourri

Reducing Startup Time in Co-Designed Virtual Machines (Abstract)

James E. Smith , University of Wisconsin
Shiliang Hu , University of Wisconsin
pp. 277-288

TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time (Abstract)

Jin Ren , University of Rhode Island
Weijun Xiao , University of Rhode Island
Qing Yang , University of Rhode Island
pp. 289-301
Session 8A: Dataflow

Area-Performance Trade-offs in Tiled Dataflow Architectures (Abstract)

Andrew Petersen , University of Washington
Ken Michelson , University of Washington
Martha Mercaldi , University of Washington
Steven Swanson , University of Washington
Andrew Putnam , University of Washington
Susan J. Eggers , University of Washington
Martha Mercaldi , University of Washington
Andrew Schwerin , University of Washington
Mark Oskin , University of Washington
pp. 314-326
Session 8B: Cache Coherence

Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors (Abstract)

Xiaowei Shen , IBM T. J. Watson Research Center
Josep Torrellas , University of Illinois, Urbana-Champaign
Karin Strauss , University of Illinois, Urbana-Champaign
pp. 327-338

Interconnect-Aware Coherence Protocols for Chip Multiprocessors (Abstract)

Rajeev Balasubramonian , University of Utah
John B. Carter , University of Utah
Liqun Cheng , University of Utah
Naveen Muralimanohar , University of Utah
Karthik Ramani , University of Utah
pp. 339-351
Keynote 3
Session 9: Quantum Computing

Distributed Arithmetic on a Quantum Multicomputer (Abstract)

Kohei M. Itoh , Keio University and CREST-JST
Rodney Van Meter , Keio University and CREST-JST
Kae Nemoto , National Institute of Informatics, Japan
W. J. Munro , Hewlett-Packard Laboratories, UK
pp. 354-365

Interconnection Networks for Scalable Quantum Computers (Abstract)

Yatish Patel , University of California, Berkeley
Mark Whitney , University of California, Berkeley
John Kubiatowicz , University of California, Berkeley
Nemanja Isailovic , University of California, Berkeley
pp. 366-377

Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing (Abstract)

Tzvetan S. Metodi , University of California at Davis
Frederic T. Chong , University of California at Santa Barbara
Darshan D. Thaker , University of California at Davis
Andrew W. Cross , Massachusetts Institute of Technology
Isaac L. Chuang , Massachusetts Institute of Technology
pp. 378-390
Author Index

Author Index (PDF)

pp. 391
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