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Computer Architecture, International Symposium on (2006)
Boston, Massachusetts
June 17, 2006 to June 21, 2006
ISSN: 1063-6897
ISBN: 0-7695-2608-X
pp: 53-65
Christos Kozyrakis , Stanford University
Chi Cao Minh , Stanford University
Brian D. Carlstrom , Stanford University
Kunle Olukotun , Stanford University
Hassan Chafi , Stanford University
JaeWoong Chung , Stanford University
Austen McDonald , Stanford University
ABSTRACT
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional state buffering and conflict resolution. Missing is a robust hardware/software interface, not limited to simplistic instructions defining transaction boundaries. Without rich semantics, current TM systems cannot support basic features of modern programming languages and operating systems such as transparent library calls, conditional synchronization, system calls, I/O, and runtime exceptions. This paper presents a comprehensive instruction set architecture (ISA) for TM systems. Our proposal introduces three key mechanisms: two-phase commit; support for software handlers on commit, violation, and abort; and full support for open- and closed-nested transactions with independent rollback. These mechanisms provide a flexible interface to implement programming language and operating system functionality. We also show that these mechanisms are practical to implement at the ISA and microarchitecture level for various TM systems. Using an execution-driven simulation, we demonstrate both the functionality (e.g., I/O and conditional scheduling within transactions) and performance potential (2.2? improvement for SPECjbb2000) of the proposed mechanisms. Overall, this paper establishes a rich and efficient interface to foster both hardware and software research on transactional memory.
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CITATION
Christos Kozyrakis, Chi Cao Minh, Brian D. Carlstrom, Kunle Olukotun, Hassan Chafi, JaeWoong Chung, Austen McDonald, "Architectural Semantics for Practical Transactional Memory", Computer Architecture, International Symposium on, vol. 00, no. , pp. 53-65, 2006, doi:10.1109/ISCA.2006.9
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