The Community for Technology Leaders
Computer Architecture, International Symposium on (2005)
Madison, Wisconsin
June 4, 2005 to June 8, 2005
ISSN: 1063-6897
ISBN: 0-7695-2270-X
TABLE OF CONTENTS
Introduction

list-reviewer (PDF)

pp. xvii,xviii

Committees (PDF)

pp. xvi
Session 1: Security

Architecture for Protecting Critical Secrets in Microprocessors (Abstract)

Ruby B. Lee , Princeton University
Zhenghong Wang , Princeton University
Peter C. S. Kwan , Princeton University
John P. McGregor , Princeton University
Jeffrey Dwoskin , Princeton University
pp. 2-13

High Efficiency Counter Mode Security Architecture via Prediction and Precomputation (Abstract)

Hsien-Hsin S. Lee , Georgia Institute of Technology
Chenghuai Lu , Georgia Institute of Technology
Mrinmoy Ghosh , Georgia Institute of Technology
Weidong Shi , Georgia Institute of Technology
Alexandra Boldyreva , Georgia Institute of Technology
pp. 14-24

Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions (Abstract)

Charles W. O?Donnell , Massachusetts Institute of Technology
G. Edward Suh , Massachusetts Institute of Technology
Ishan Sachdev , Massachusetts Institute of Technology
Srinivas Devadas , Massachusetts Institute of Technology
pp. 25-36
Session 2a: Interacting with Disks and Networks

Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management (Abstract)

Sudhanva Gurumurthi , Pennsylvania State University
Anand Sivasubramaniam , Pennsylvania State University
Vivek K. Natarajan , Pennsylvania State University
pp. 38-49

Direct Cache Access for High Bandwidth Network I/O (Abstract)

Ram Huggahalli , Intel Corporation
Scott Tetrick , Intel Corporation
Ravi Iyer , Intel Corporation
pp. 50-59

Deconstructing Commodity Storage Clusters (Abstract)

Haryadi S. Gunawi , University of Wisconsin - Madison
Andrea C. Arpaci-Dusseau , University of Wisconsin - Madison
Remzi H. Arpaci-Dusseau , University of Wisconsin - Madison
Nitin Agrawal , University of Wisconsin - Madison
Jiri Schindler , EMC Corporation
pp. 60-71
Session 2b: Memory Compression and Renamer Optimizations

Continuous Optimization (Abstract)

pp. 86-97
Session 3a: Specialized Processors

A High Throughput String Matching Architecture for Intrusion Detection and Prevention (Abstract)

Lin Tan , University of California at Santa Barbara
Timothy Sherwood , University of California at Santa Barbara
pp. 112-122

A Tree Based Router Search Engine Architecture with Single Port Memories (Abstract)

Sumeet Singh , University of California at San Diego
Grigore Rosu , University of Illinois at Urbana-Champaign
Florin Baboescu , University of California at San Diego
Dean M. Tullsen , University of California at San Diego
pp. 123-133
Session 3b: Detecting Faults

Design and Evaluation of Hybrid Fault-Detection Systems (Abstract)

Ram Rangan , Princeton University
Shubhendu S. Mukherjee , Intel Massachusetts
Jonathan Chang , Princeton University
David I. August , Princeton University
Neil Vachharajani , Princeton University
George A. Reis , Princeton University
pp. 148-159

Opportunistic Transient-Fault Detection (Abstract)

T. N. Vijaykumar , Purdue University
Mohamed A. Gomaa , Purdue University
pp. 172-183
Session 4a: Quantum Computing and Very Low Power

An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures (Abstract)

Lucas Kregor-Stickles , University of Washington
Steven Balensiefer , University of Washington
Mark Oskin , University of Washington
pp. 186-196
Session 4a: Quantum Computing and Very Low Power

An Ultra Low Power System Architecture for Sensor Network Applications (Abstract)

Nikhil Tripathi , Harvard University
David Brooks , Harvard University
Mark Hempstead , Harvard University
Gu-Yeon Wei , Harvard University
Patrick Mauro , Harvard University
pp. 208-219
Session 4b: Coherence

Temporal Streaming of Shared Memory (Abstract)

Babak Falsafi , Carnegie Mellon University
Stephen Somogyi , Carnegie Mellon University
Thomas F. Wenisch , Carnegie Mellon University
Jangwoo Kim , Carnegie Mellon University
Anastassia Ailamaki , Carnegie Mellon University
Nikolaos Hardavellas , Carnegie Mellon University
pp. 222-233

Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking (Abstract)

James E. Smith , University of Wisconsin - Madison
Mikko H. Lipasti , University of Wisconsin - Madison
Jason F. Cantin , University of Wisconsin - Madison
pp. 246-257
Session 5a: Applying Compilers and Debugging Support

Improving Program Efficiency by Packing Instructions into Registers (Abstract)

Stephen Hines , Florida State University
Joshua Green , Florida State University
David Whalley , Florida State University
Gary Tyson , Florida State University
pp. 260-271

An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors (Abstract)

Scott Mahlke , University of Michigan - Ann Arbor
Kriszti? Flautner , ARM, Ltd.
Nathan Clark , University of Michigan - Ann Arbor
Stuart Biles , ARM, Ltd.
Jason Blome , University of Michigan - Ann Arbor
Michael Chu , University of Michigan - Ann Arbor
pp. 272-283

BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging (Abstract)

Satish Narayanasamy , University of California at San Diego
Brad Calder , University of California at San Diego
Gilles Pokam , University of California at San Diego
pp. 284-295
Session 5b: Power

Mitigating Amdahl?s Law through EPI Throttling (Abstract)

Murali Annavaram , Intel Corporation
John Shen , Intel Corporation
Ed Grochowski , Intel Corporation
pp. 298-309

Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines (Abstract)

Diana Marculescu , Carnegie Mellon University
Emil Talpes , Carnegie Mellon University
pp. 310-321

Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection (Abstract)

Amir Roth , University of Pennsylvania
Vlad Petric , University of Pennsylvania
pp. 322-333
Session 6a: Chip Multiprocessor Memory Hierarchies

Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors (Abstract)

Michael Zhang , Massachusetts Institute of Technology
Krste Asanović , Massachusetts Institute of Technology
pp. 336-345

Optimizing Replication, Communication, and Capacity Allocation in CMPs (Abstract)

Michael D. Powell , Purdue University
Zeshan Chishti , Purdue University
T. N. Vijaykumar , Purdue University
pp. 357-368
Session 6b: Runahead and Branch Prediction

Techniques for Efficient Processing in Runahead Execution Engines (Abstract)

Yale N. Patt , University of Texas at Austin
Onur Mutlu , University of Texas at Austin
Hyesoon Kim , University of Texas at Austin
pp. 370-381

Piecewise Linear Branch Prediction (Abstract)

Daniel A. Jiménez , Rutgers University
pp. 382-393
Session 7a: Interconnection Networks

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling (Abstract)

Dean M. Tullsen , University of California at San Diego
Victor Zyuban , IBM TJ Watson Research Center
Rakesh Kumar , University of California at San Diego
pp. 408-419

Microarchitecture of a High-Radix Router (Abstract)

William J. Dally , Stanford University
Amit K. Gupta , Stanford University
John Kim , Stanford University
Brian Towles , D.E. Shaw Research and Development
pp. 420-431

Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks (Abstract)

Mithuna Thottethodi , Purdue University
Nauman Rafique , Purdue University
Akif Ali , Purdue University
Daeho Seo , Purdue University
Won-Taek Lim , Purdue University
pp. 432-443
Session 7b: Load and Store Queues

Scalable Load and Store Processing in Latency Tolerant Processors (Abstract)

Ravi Rajwar , Intel Corporation
Haitham Akkary , Intel Corporation
Srikanth T. Srinivasan , Intel Corporation
Amit Gandhi , Portland State University
Konrad Lai , Intel Corporation
pp. 446-457

Store Buffer Design in First-Level Multibanked Data Caches (Abstract)

P. Iba? , University de Zaragoza
J. M. Llaber? , University Polit?cnica de Catalunya
E. F. Torres , University de Zaragoza
V. Vi?als , University de Zaragoza
pp. 469-480
Session 8a: Multiprocessor Issues

Dynamic Verification of Sequential Consistency (Abstract)

Daniel J. Sorin , Duke University
Albert Meixner , Duke University
pp. 482-493

Virtualizing Transactional Memory (Abstract)

Konrad Lai , Intel Corporation
Maurice Herlihy , Brown University
Ravi Rajwar , Intel Corporation
pp. 494-505

The Impact of Performance Asymmetry in Emerging Multicore Architectures (Abstract)

Mike Upton , Intel Corporation
Konrad Lai , Intel Corporation
Ravi Rajwar , Intel Corporation
Saisanthosh Balakrishnan , University of Wisconsin-Madison
pp. 506-517
Session 8b: Reliability and a Cache Organization

Exploiting Structural Duplication for Lifetime Reliability Enhancement (Abstract)

Pradip Bose , IBM T.J. Watson Research Center
Sarita V. Adve , University of Illinois at Urbana-Champaign
Jude A. Rivers , IBM T.J. Watson Research Center
Jayanth Srinivasan , University of Illinois at Urbana-Champaign
pp. 520-531

Computing Architectural Vulnerability Factors for Address-Based Structures (Abstract)

Razvan Cheveresan , Sun Microsystems
Joel Emer , Intel Corp.
Ram Rangan , Princeton University
Paul Racunas , Intel Corp.
Arijit Biswas , Intel Corp.
pp. 532-543

The V-Way Cache: Demand Based Associativity via Global Replacement (Abstract)

Yale N. Patt , University of Texas at Austin
David Thompson , University of Texas at Austin
Moinuddin K. Qureshi , University of Texas at Austin
pp. 544-555
Author Index

Author Index (PDF)

pp. 556-557
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