The Community for Technology Leaders
Computer Architecture, International Symposium on (2004)
M?nchen, Germany
June 19, 2004 to June 23, 2004
ISSN: 1063-6897
ISBN: 0-7695-2143-6
TABLE OF CONTENTS

Committees (PDF)

pp. xi

Reviewers (PDF)

pp. xiii
Keynote 1
Session 1: Architecture Evaluations

Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams (Abstract)

Henry Hoffmann , CSAIL, Massachusetts Institute of Technology
James Psota , CSAIL, Massachusetts Institute of Technology
Ian Bratt , CSAIL, Massachusetts Institute of Technology
Michael Bedford Taylor , CSAIL, Massachusetts Institute of Technology
Matt Frank , CSAIL, Massachusetts Institute of Technology
Nathan Shnidman , CSAIL, Massachusetts Institute of Technology
Anant Agarwal , CSAIL, Massachusetts Institute of Technology
Ben Greenwald , CSAIL, Massachusetts Institute of Technology
Jason Kim , CSAIL, Massachusetts Institute of Technology
Volker Strumpen , CSAIL, Massachusetts Institute of Technology
Saman Amarasinghe , CSAIL, Massachusetts Institute of Technology
Arvind Saraf , CSAIL, Massachusetts Institute of Technology
Jason Miller , CSAIL, Massachusetts Institute of Technology
David Wentzlaff , CSAIL, Massachusetts Institute of Technology
Walter Lee , CSAIL, Massachusetts Institute of Technology
Paul Johnson , CSAIL, Massachusetts Institute of Technology
pp. 2

Evaluating the Imagine Stream Architecture (Abstract)

William J. Dally , Stanford University, CA
Brucek Khailany , Stanford University, CA
Abhishek Das , Stanford University, CA
Ujval J. Kapasi , Stanford University, CA
Jung Ho Ahn , Stanford University, CA
pp. 14

Field-testing IMPACT EPIC research results in Itanium 2 (Abstract)

Ian M. Steiner , University of Illinois at Urbana-Champaign
Erik M. Nystrom , University of Illinois at Urbana-Champaign
Wen-mei W. Hwu , University of Illinois at Urbana-Champaign
Geoff A. Kent , University of Illinois at Urbana-Champaign
Sain-zee Ueng , University of Illinois at Urbana-Champaign
John W. Sias , University of Illinois at Urbana-Champaign
pp. 26
Session 2A: Parallelism in Microarchitectures

The Vector-Thread Architecture (Abstract)

Ronny Krashinsky , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Christopher Batten , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Jared Casper , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Brian Pharris , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Steve Gerding , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Krste Asanovic , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
Mark Hampton , MIT Computer Science and Artificial Intelligence Laboratory, Cambridge, MA
pp. 52

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance (Abstract)

Parthasarathy Ranganathan , HP Labs, Palo Alto, CA
Dean M. Tullsen , University of California, San Diego
Norman P. Jouppi , HP Labs, Palo Alto, CA
Rakesh Kumar , University of California, San Diego
Keith I. Farkas , HP Labs, Palo Alto, CA
pp. 64

Microarchitecture Optimizations for Exploiting Memory-Level Parallelism (Abstract)

Yuan Chou , Sun Microsystems, Sunnyvale, CA
Santosh Abraham , Sun Microsystems, Sunnyvale, CA
Brian Fahs , Sun Microsystems, Sunnyvale, CA
pp. 76
Session 2B: Memory Consistency

Memory Ordering: A Value-Based Approach (Abstract)

Mikko H. Lipasti , Univ. of Wisconsin-Madison
Harold W. Cain , Univ. of Wisconsin-Madison
pp. 90

Transactional Memory Coherence and Consistency (Abstract)

Ben Hertzberg , Stanford University
Vicky Wong , Stanford University
Mike Chen , Stanford University
Brian D. Carlstrom , Stanford University
Christos Kozyrakis , Stanford University
Honggo Wijaya , Stanford University
Manohar K. Prabhu , Stanford University
Kunle Olukotun , Stanford University
John D. Davis , Stanford University
Lance Hammond , Stanford University
pp. 102

TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model (Abstract)

Sridhar , Sun Microsystems, Sunnyvale, CA
Chaiyasit Manovit , Sun Microsystems, Sunnyvale, CA
Durgam Vahia , Sun Microsystems, Sunnyvale, CA
Sudheendra Hangal , Sun Microsystems India Private Limited, Bangalore, India
Juin-Yeu Joseph Lu , Sun Microsystems, Sunnyvale, CA
pp. 114

SMTp: An Architecture for Next-generation Scalable Multi-threading (Abstract)

Mainak Chaudhuri , Cornell University, Ithaca, NY
Mark Heinrich , University of Central Florida
pp. 124
Panel: Supporting ILP in Tiled Architectures: Wasted Effort, or a Good Idea?

null (PDF)

pp. null
Keynote 2
Session 3A: Power and Energy

A Formal Approach to Frequent Energy Adaptations for Multimedia Applications (Abstract)

Sarita V. Adve , University of Illinois at Urbana-Champaign
Christopher J. Hughes , Intel Corporation
pp. 138

Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor (Abstract)

Venkatesh Akella , University of California, Davis
Jedidiah Crandall , University of California, Davis
Diana Franklin , California Polytechnic State University, San Luis Obispo
Leslie W. Jones IV , California Polytechnic State University, San Luis Obispo
Ravishankar Rao , University of California, Davis
Paul Sultana , University of California, Davis
John Oliver , University of California, Davis
Erik Czernikowski , University of California, Davis
Frederic T. Chong , University of California, Davis
pp. 150

Power Awareness through Selective Dynamically Optimized Traces (Abstract)

Naftali Schwartz , Intel Labs, Haifa, Israel
Micha Moffie , Intel Labs, Haifa, Israel
Yoav Almog , Intel Labs, Haifa, Israel
Roni Rosner , Intel Labs, Haifa, Israel
Avi Mendelson , Intel Labs, Haifa, Israel
pp. 162
Session 3B: Interconnect and I/O

X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs (Abstract)

Remzi H. Arpaci-Dusseau , University of Wisconsin-Madison
Andrea C. Arpaci-Dusseau , University of Wisconsin-Madison
Muthian Sivathanu , University of Wisconsin-Madison
Lakshmi N. Bairavasundaram , University of Wisconsin-Madison
pp. 176

Low-Latency Virtual-Channel Routers for On-Chip Networks (Abstract)

Andrew West , University of Cambridge, UK
Robert Mullins , University of Cambridge, UK
Simon Moore , University of Cambridge, UK
pp. 188

Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism (Abstract)

J. A. Gregorio , University of Cantabria, Spain
R. Beivide , University of Cantabria, Spain
V. Puente , University of Cantabria, Spain
F. Vallejo , University of Cantabria, Spain
pp. 198
Session 4A: Compression and Debugging

Adaptive Cache Compression for High-Performance Processors (Abstract)

Alaa R. Alameldeen , University of Wisconsin-Madison
David A. Wood , University of Wisconsin-Madison
pp. 212

iWatcher: Efficient Architectural Support for Software Debugging (Abstract)

Josep Torrellas , University of Illinois at Urbana-Champaign
Feng Qin , University of Illinois at Urbana-Champaign
Yuanyuan Zhou , University of Illinois at Urbana-Champaign
Pin Zhou , University of Illinois at Urbana-Champaign
Wei Liu , University of Illinois at Urbana-Champaign
pp. 224
Session 4B: Superscalars

Prophet/Critic Hybrid Branch Prediction (Abstract)

Ayose Falc? , Universitat Polit?cnica de Catalunya
Alex Ramirez , Universitat Polit?cnica de Catalunya
Konrad Lai , Intel Corporation
Jared Stark , Intel Corporation
Mateo Valero , Universitat Polit?cnica de Catalunya
pp. 250
Session 5A: Support for Reliability

Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor (Abstract)

Shubhendu S. Mukherjee , Intel Corporation, Hudson MA
Christopher Weaver , Intel Corporation, Hudson MA
Steven K. Reinhardt , Intel Corporation, Hudson MA; University of Michigan, Ann Arbor
Joel Emer , Intel Corporation, Hudson MA
pp. 264

The Case for Lifetime Reliability-Aware Microprocessors (Abstract)

Jude A. Rivers , IBM T.J. Watson Research Center, Yorktown Heights, NY
Sarita V. Adve , University of Illinois at Urbana-Champaign
Pradip Bose , IBM T.J. Watson Research Center, Yorktown Heights, NY
Jayanth Srinivasan , University of Illinois at Urbana-Champaign
pp. 276
Session 5B: Register File

Use-Based Register Caching with Decoupled Indexing (Abstract)

Gurindar S. Sohi , University of Wisconsin-Madison
J. Adam Butts , University of Wisconsin-Madison
pp. 302

A Content Aware Integer Register File Organization (Abstract)

Alexander Veidenbaum , University of California, Irvine
Adri? Cristal , Universitat Polit?nica de Catalunya
Mateo Valero , Universitat Polit?nica de Catalunya
Daniel Ortega , HP Labs Barcelona
Rub?n Gonz?lez , Universitat Polit?nica de Catalunya
pp. 314

Physical Register Inlining (Abstract)

Erika Gunadi , University of Wisconsin-Madison
Mikko H. Lipasti , University of Wisconsin-Madison
Brian R. Mestan , IBM Corporation - Austin, TX
pp. 325
Session 6A: Performance Methodologies

A First-Order Superscalar Processor Model (Abstract)

James E. Smith , Univ. of Wisconsin - Madison
Tejas S. Karkhanis , Univ. of Wisconsin - Madison
pp. 338

Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies (Abstract)

Bastiaan Stougie , Ghent University, Belgium
Robert H. Bell Jr. , The University of Texas at Austin
Koen De Bosschere , Ghent University, Belgium
Lizy K. John , The University of Texas at Austin
Lieven Eeckhout , Ghent University, Belgium
pp. 350
Session 6B: Microarchitectural Concepts

Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs (Abstract)

Bruce Jacob , University of Maryland, College Park
Sadagopan Srinivasan , University of Maryland, College Park
Bharath Iyer , University of Maryland, College Park
pp. 364

A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy (Abstract)

Angshuman Parashar , The Pennsylvania State University
Anand Sivasubramaniam , The Pennsylvania State University
Sudhanva Gurumurthi , The Pennsylvania State University
pp. 376

Author Index (PDF)

pp. 387
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