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Computer Architecture, International Symposium on (2004)
M?nchen, Germany
June 19, 2004 to June 23, 2004
ISSN: 1063-6897
ISBN: 0-7695-2143-6
pp: 2
Michael Bedford Taylor , CSAIL, Massachusetts Institute of Technology
Walter Lee , CSAIL, Massachusetts Institute of Technology
Jason Miller , CSAIL, Massachusetts Institute of Technology
David Wentzlaff , CSAIL, Massachusetts Institute of Technology
Ian Bratt , CSAIL, Massachusetts Institute of Technology
Ben Greenwald , CSAIL, Massachusetts Institute of Technology
Henry Hoffmann , CSAIL, Massachusetts Institute of Technology
Paul Johnson , CSAIL, Massachusetts Institute of Technology
Jason Kim , CSAIL, Massachusetts Institute of Technology
James Psota , CSAIL, Massachusetts Institute of Technology
Arvind Saraf , CSAIL, Massachusetts Institute of Technology
Nathan Shnidman , CSAIL, Massachusetts Institute of Technology
Volker Strumpen , CSAIL, Massachusetts Institute of Technology
Matt Frank , CSAIL, Massachusetts Institute of Technology
Saman Amarasinghe , CSAIL, Massachusetts Institute of Technology
Anant Agarwal , CSAIL, Massachusetts Institute of Technology
ABSTRACT
This paper evaluates the Raw microprocessor. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existing ILP-based sequential programs with reasonable performance in the face of increasing wire delays. Raw approaches this challenge by implementing plenty of on-chip resources - including logic, wires, and pins - in a tiled arrangement, and exposing them through a new ISA, so that the software can take advantage of these resources for parallel applications. Raw supports both ILP and streams by routing operands between architecturally-exposed functional units over a point-to-point scalar operand network. This network offers low latency for scalar data transport. Raw manages the effect of wire delays by exposing the interconnect and using software to orchestrate both scalar and stream data transport.<div></div> We have implemented a prototype Raw microprocessor in IBM's 180 nm, 6-layer copper, CMOS 7SF standard-cell ASIC process. We have also implemented ILP and stream compilers. Our evaluation attempts to determine the extent to which Raw succeeds in meeting its goal of serving as a more versatile, general-purpose processor. Central to achieving this goal is Raw's ability to exploit all forms of parallelism, including ILP, DLP, TLP, and Stream parallelism. Specifically, we evaluate the performance of Raw on a diverse set of codes including traditional sequential programs, streaming applications, server workloads and bit-level embedded computation. Our experimental methodology makes use of a cycle-accurate simulator validated against our real hardware. Compared to a 180 nm Pentium-III, using commodity PC memory system components, Raw performs within a factor of 2x for sequential applications with a very low degree of ILP, about 2x to 9x better for higher levels of ILP, and 10x-100x better when highly parallel applications are coded in a stream language or optimized by hand. The paper also proposes a new versatility metric and uses it to discuss the generality of Raw.
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CITATION

H. Hoffmann et al., "Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams," Computer Architecture, International Symposium on(ISCA), M?nchen, Germany, 2004, pp. 2.
doi:10.1109/ISCA.2004.1310759
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