The Community for Technology Leaders
Computer Architecture, International Symposium on (2003)
San Diego, California
June 9, 2003 to June 11, 2003
ISSN: 1063-6897
ISBN: 0-7695-1945-8
TABLE OF CONTENTS
Session 1: Thermal and Energy-Aware Microarchitectures

Temperature-Aware Microarchitecture (Abstract)

Wei Huang , University of Virginia
David Tarjan , University of Virginia
Karthik Sankaranarayanan , University of Virginia
Sivakumar Velusamy , University of Virginia
Mircea R. Stan , University of Virginia
Kevin Skadron , University of Virginia
pp. 2

Profile-based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor (Abstract)

Greg Semeraro , University of Rochester
Grigorios Magklis , University of Rochester
David H. Albonesi , University of Rochester
Michael L. Scott , University of Rochester
Steven Dropsho , University of Rochester
pp. 14
Session 2: Processor Architecture

Half-Price Architecture (Abstract)

Mikko H. Lipasti , University of Wisconsin-Madison
Ilhyun Kim , University of Wisconsin-Madison
pp. 28

Implicitly-Multithreaded Processors (Abstract)

T. N. Vijaykumar , Purdue University
Il Park , Purdue University
Babak Falsafi , Carnegie Mellon University
pp. 39
Panel: Subsetting SPEC When Measuring Results: Valid or Manipulative?

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Session 3a: Microarchitecture Techniques

Banked Multiported Register Files for High-Frequency Superscalar Microprocessors (Abstract)

Jessica H. Tseng , MIT Laboratory for Computer Science
Krste Asanovic , MIT Laboratory for Computer Science
pp. 62

SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling (Abstract)

Babak Falsafi , Carnegie Mellon University
Thomas F. Wenisch , Carnegie Mellon University
James C. Hoe , Carnegie Mellon University
Roland E. Wunderlich , Carnegie Mellon University
pp. 84
Session 3b: Recovery and Replay

Transient-Fault Recovery for Chip Multiprocessors (Abstract)

T. N. Vijaykumar , Purdue University
Irith Pomeranz , Purdue University
Chad Scarbrough , Purdue University
Mohamed Gomaa , Purdue University
pp. 98

ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes (Abstract)

Milos Prvulovic , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
pp. 110

A "Flight Data Recorder" for Enabling Full-system Multiprocessor Deterministic Replay (Abstract)

Rastislav Bodik , Univ. of Wisconsin-Madison; Univ. of California, Berkeley; IBM T.J. Watson Research Center
Mark D. Hill , Univ. of Wisconsin-Madison; Universitat Polit?cnica de Catalunya (UPC)
Min Xu , Univ. of Wisconsin-Madison
pp. 122
Session 4a: Energy-Saving Designs

A Highly Configurable Cache Architecture for Embedded Systems (Abstract)

Chuanjun Zhang , University of California, Riverside
Frank Vahid , University of California, Riverside
Walid Najjar , University of California, Riverside
pp. 136

Energy Efficient Co-Adaptive Instruction Fetch and Issue (Abstract)

Alper Buyuktosunoglu , University of Rochester
Tejas Karkhanis , University of Wisconsin-Madison
Pradip Bose , IBM T.J. Watson Research Center
David H. Albonesi , University of Rochester
pp. 147

Positional Adaptation of Processors: Application to Energy Reduction (Abstract)

Jose Renau , University of Illinois at Urbana-Champaign
Michael C. Huang , University of Rochester
Josep Torrellas , University of Illinois at Urbana-Champaign
pp. 157

DRPM: Dynamic Speed Control for Power Management in Server Class Disks (Abstract)

Sudhanva Gurumurthi , The Pennsylvania State University
Anand Sivasubramaniam , The Pennsylvania State University
Hubertus Franke , Thomas J. Watson Research Center
Mahmut Kandemir , The Pennsylvania State University
pp. 169
Session 4b: Interconnects and Multiprocessors

Token Coherence: Decoupling Performance and Correctness (Abstract)

Mark D. Hill , University of Wisconsin-Madison
Milo M. K. Martin , University of Wisconsin-Madison
David A. Wood , University of Wisconsin-Madison
pp. 182

GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks (Abstract)

Amit K Gupta , Stanford University
Arjun Singh , Stanford University
Brian Towles , Stanford University
William J Dally , Stanford University
pp. 194

Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors (Abstract)

Mark D. Hill , University of Wisconsin-Madison
Milo M. K. Martin , University of Wisconsin-Madison
Pacia J. Harper , University of Wisconsin-Madison
David A. Wood , University of Wisconsin-Madison
Daniel J. Sorin , Duke University
pp. 206
Session 5: Front-End Scheduling

Parallelism in the Front-End (Abstract)

Gurindar S. Sohi , University of Wisconsin-Madison
Paramjit S. Oberoi , University of Wisconsin-Madison
pp. 230

Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay (Abstract)

Dan Ernst , University of Michigan
Andrew Hamel , University of Michigan
Todd Austin , University of Michigan
pp. 253
Session 6a: Clustered Processors

Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors (Abstract)

Ravi Bhargava , The University of Texas at Austin
Lizy K. John , The University of Texas at Austin
pp. 264
Session 6b: Network Processors

A Pipelined Memory Architecture for High Throughput Network Processors (Abstract)

Timothy Sherwood , University of California, San Diego
Brad Calder , University of California, San Diego
George Varghese , University of California, San Diego
pp. 288
Session 7a: Prediction

Improving Branch Prediction by Dynamic Dataflow-based Identification of Correlated Branches from a Large Global History (Abstract)

Renju Thomas , University of Maryland, College Park
Manoj Franklin , University of Maryland, College Park
Chris Wilkerson , Intel Corporation
Jared Stark , Intel Labs
pp. 314

Detecting Global Stride Locality in Value Streams (Abstract)

Thomas M. Conte , North Carolina State University
Huiyang Zhou , North Carolina State University
Jill Flanagan , North Carolina State University
pp. 324

Phase Tracking and Prediction (Abstract)

Suleyman Sair , University of California, San Diego
Brad Calder , University of California, San Diego
Timothy Sherwood , University of California, San Diego
pp. 336
Session 7b: Mechanisms and Support

Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems (Abstract)

Kiran Seth , North Carolina State Univ.
Kaustubh Patil , North Carolina State Univ.
Aravindh Anantaraman , North Carolina State Univ.
Eric Rotenberg , North Carolina State Univ.
Frank Mueller , North Carolina State Univ.
pp. 350

DISE: A Programmable Macro Engine for Customizing Applications (Abstract)

E Christopher Lewis , University of Pennsylvania
Marc L. Corliss , University of Pennsylvania
Amir Roth , University of Pennsylvania
pp. 362

Building Quantum Wires: The Long and the Short of it (Abstract)

Mark Oskin , University of Washington
John Kubiatowicz , University of California, Berkeley
Frederic T. Chong , University of California, Davis
Isaac L. Chuang , Massachusetts Institute of Technology
pp. 374
Session 8: Memory Issues

Guided Region Prefetching: A Cooperative Hardware/Software Approach (Abstract)

Doug Burger , The University of Texas at Austin
Steven K. Reinhardt , University of Michigan
Charles C. Weems , Univ. of Massachusetts, Amherst
Zhenlin Wang , Univ. of Massachusetts, Amherst
Kathryn S. McKinley , The University of Texas at Austin
pp. 388

Overcoming the Limitations of Conventional Vector Processors (Abstract)

David Patterson , University of California at Berkeley
Christos Kozyrakis , Stanford University
pp. 399

A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels (Abstract)

Eun-Gyu Kim , University of Southern California/Information Sciences Institute
Matthew C. French , University of Southern California/Information Sciences Institute
Stephen P. Crago , University of Southern California/Information Sciences Institute
Jinwoo Suh , University of Southern California/Information Sciences Institute
Lakshmi Srinivasan , University of Southern California/Information Sciences Institute
pp. 410
Session 9: Exploiting Parallelisms

Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture (Abstract)

Stephen W. Keckler , The University of Texas at Austin
Haiming Liu , The University of Texas at Austin
Charles R. Moore , The University of Texas at Austin
Changkyu Kim , The University of Texas at Austin
Jaehyuk Huh , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
Ramadass Nagarajan , The University of Texas at Austin
Karthikeyan Sankaralingam , The University of Texas at Austin
pp. 422

The Jrpm System for Dynamically Parallelizing Java Programs (Abstract)

Kunle Olukotun , Stanford University
Michael K. Chen , Stanford University
pp. 434

Author's Index (PDF)

pp. 447
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