Computer Architecture, International Symposium on (2003)
San Diego, California
June 9, 2003 to June 11, 2003
Milo M. K. Martin , University of Wisconsin-Madison
Mark D. Hill , University of Wisconsin-Madison
David A. Wood , University of Wisconsin-Madison
Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated "glueless" designs. Implementing low-latency cache coherence in these systems is difficult, because traditional approaches either add indirection for common cache-to-cache misses (directory protocols) or require a totally-ordered interconnect (traditional snooping protocols). Unfortunately, totally-ordered interconnects are difficult to implement in glueless designs. An ideal coherence protocol would avoid indirections and interconnect ordering; however, such an approach introduces numerous protocol races that are difficult to resolve.<div></div> We propose a new coherence framework to enable such protocols by separating performance from correctness. A performance protocol can optimize for the common case (i.e., absence of races) and rely on the underlying correctness substrate to resolve races, provide safety, and prevent starvation. We call the combination Token Coherence, since it explicitly exchanges and counts tokens to control coherence permissions.<div></div> This paper develops TokenB, a specific Token Coherence performance protocol that allows a glueless multiprocessor to both exploit a low-latency unordered interconnect (like directory protocols) and avoid indirection (like snooping protocols). Simulations using commercial workloads show that our new protocol can significantly outperform traditional snooping and directory protocols.
M. D. Hill, M. M. Martin and D. A. Wood, "Token Coherence: Decoupling Performance and Correctness," Computer Architecture, International Symposium on(ISCA), San Diego, California, 2003, pp. 182.