Computer Architecture, International Symposium on (2003)
San Diego, California
June 9, 2003 to June 11, 2003
T. N. Vijaykumar , Purdue University
Il Park , Purdue University
Babak Falsafi , Carnegie Mellon University
This paper proposes the Implicitly-MultiThreaded (IMT) architecture to execute compiler-specified speculative threads on to a modified Simultaneous Multithreading pipeline. IMT reduces hardware complexity by relying on the compiler to select suitable thread spawning points and orchestrate inter-thread register communication. To enhance IMT?s effectiveness, this paper proposes three novel microarchitectural mechanisms: (1) resource- and dependence-based fetch policy to fetch and execute suitable instructions, (2) context multiplexing to improve utilization and map as many threads to a single context as allowed by availability of resources, and (3) early thread-invocation to hide thread start-up overhead by overlapping one thread?s invocation with other threads? execution.<div></div> We use SPEC2K benchmarks and cycle-accurate simulation to show that an microarchitecture-optimized IMT improves performance on average by 24% and at best by 69% over an aggressive superscalar. We also compare IMT to two prior proposals, TME and DMT, for speculative threading on an SMT using hardware-extracted threads. Our best IMT design outperforms a comparable TME and DMT on average by 26% and 38% respectively.
T. N. Vijaykumar, Il Park, Babak Falsafi, "Implicitly-Multithreaded Processors", Computer Architecture, International Symposium on, vol. 00, no. , pp. 39, 2003, doi:10.1109/ISCA.2003.1206987