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Computer Architecture, International Symposium on (2002)
Anchorage, Alaska
May 25, 2002 to May 29, 2002
ISBN: 0-7695-1605-X
pp: 0099
ABSTRACT
Exponential growth in the number of on-chip transistors, coupled with reductions in voltage levels, makes each generation of microprocessors increasingly vulnerable to transient faults. In a multithreaded environment, we can detect these faults by running two copies of the same program as separate threads, feeding them identical inputs, and comparing their outputs, a technique we call Redundant Multithreading (RMT).This paper studies RMT techniques in the context of both single- and dual-processor simultaneous multithreaded (SMT) single-chip devices. Using a detailed, commercial-grade, SMT processor design we uncover subtle RMT implementation complexities, and find that RMT can be a more significant burden for single-processor devices than prior studies indicate. However, a novel application of RMT techniques in a dual-processor device, which we term chip-level redundant threading (CRT), shows higher performance than lockstepping the two cores, especially on multithreaded workloads.
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CITATION
Michael Kontz, Steven K. Reinhardt, Shubhendu S. Mukherjee, "Detailed Design and Evaluation of Redundant Multithreading Alternatives", Computer Architecture, International Symposium on, vol. 00, no. , pp. 0099, 2002, doi:10.1109/ISCA.2002.1003566
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