The Community for Technology Leaders
Computer Architecture, International Symposium on (2001)
G?teborg, Sweden
June 30, 2001 to July 4, 2001
ISBN: 0-7695-1162-7
TABLE OF CONTENTS

Reviewers (PDF)

pp. x
Plenary Session

Opening Remarks (PDF)

pp. null

Keynote Speech (PDF)

pp. null
Session 1: Multithreading and Speculation

Execution-Based Prediction Using Speculative Slices (Abstract)

Gurindar Sohi , University of Wisconsin - Madison
Craig Zilles , University of Wisconsin - Madison
pp. 0002

Speculative Precomputation: Long-Range Prefetching of Delinquent Loads (Abstract)

Dean M. Tullsen , University of California, San Diego
John P. Shen , Intel Corporation
Jamison D. Collins , University of California, San Diego
Christopher Hughes , University of Illinois at Urbana-Champaign
Yong-Fong Lee , Intel Corporation
Hong Wang , Intel Corporation
Dan Lavery , Intel Corporation
pp. 0014

Dynamically Allocating Processor Resources between Nearby and Distant ILP (Abstract)

David H. Albonesi , University of Rochester
Sandhya Dwarkadas , University of Rochester
Rajeev Balasubramonian , University of Rochester
pp. 0026
Session 2: Memory System Issues

Data Prefetching by Dependence Graph Precomputation (Abstract)

Murali Annavaram , The University of Michigan, Ann Arbor
Edward S. Davidson , The University of Michigan, Ann Arbor
Jignesh M. Patel , The University of Michigan, Ann Arbor
pp. 0052

Concurrency, Latency, or System Overhead: Which Has the Largest Impact on Uniprocessor DRAM-System Performance? (Abstract)

Vinodh Cuppu , University of Maryland, College Park
Bruce Jacob , University of Maryland, College Park
pp. 0062
Session 3: Processor Architecture

Focusing Processor Policies via Critical-Path Prediction (Abstract)

Shai Rubin , University of Wisconsin - Madison
Rastislav Bodík , University of Wisconsin - Madison
Brian Fields , University of Wisconsin-Madison
pp. 0074

Automated Design of Finite State Machine Predictors for Customized Processors (Abstract)

Timothy Sherwood , University of California, San Diego
Brad Calder , University of California, San Diego
pp. 0086
Session 4: Communication Support

CryptoManiac: A Fast Flexible Architecture for Secure Communication (Abstract)

Todd Austin , University of Michigan
Lisa Wu , University of Michigan
Chris Weaver , University of Michigan
pp. 0110

QoS Provisioning in Clusters: An Investigation of Router and NIC Design (Abstract)

Eun Jung Kim , The Pennsylvania State University
Chita R. Das , The Pennsylvania State University
Ki Hwan Yum , The Pennsylvania State University
pp. 0120
Session 5: Cache Management

Locality vs. Criticality (Abstract)

Roy Dz-ching Ju , Intel Corporation
Srikanth T. Srinivasan , Duke University
Chris Wilkerson , Intel Corporation
Alvin R. Lebeck , Duke University
pp. 0132

Dead-Block Prediction and Dead-Block Correlating Prefetchers (Abstract)

Babak Falsafi , Carnegie Mellon University
An-Chow Lai , Purdue University
Cem Fide , Sun Microsystems
pp. 0144

Code Layout Optimizations for Transaction Processing Workloads (Abstract)

Josep Larriba-Pey , Universitat Politecnica de Catalunya
Kourosh Gharachorloo , Compaq Computer Corporation
Luiz André Barroso , Compaq Computer Corporation
P. Geoffrey Lowney , Compaq Computer Corporation
Robert Cohn , Compaq Computer Corporation
Alex Ramirez , Universitat Politecnica de Catalunya
Mateo Valero , Universitat Politecnica de Catalunya
pp. 0155
Session 6A: Architectural Impact of Emerging Technologies

Exploring and Exploiting Wire-Level Pipelining in Emerging Technologies (Abstract)

Peter M. Kogge , University of Notre Dame
Michael Thaddeus Niemier , University of Notre Dame
pp. 0166

NanoFabrics: Spatial Computing Using Molecular Electronics (Abstract)

Mihai Budiu , Carnegie Mellon University
Seth Copen Goldstein , Carnegie Mellon University
pp. 0178
Session 6B: Shared-Memory Multiprocessors

A Simple Method for Extracting Models from Protocol Code (Abstract)

David Lie , Stanford University
Andy Chou , Stanford University
Dawson Engler , Stanford University
David L. Dill , Stanford University
pp. 0192

Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization (Abstract)

María Jesús Garzarán , University of Illinois at Urbana-Champaign
Milos Prvulovic , University of Illinois at Urbana-Champaign
Lawrence Rauchwerger , Texas A&M University
Josep Torrellas , University of Illinois at Urbana-Champaign
pp. 0204
Session 7: Energy-Effective Designs

Power and Energy Reduction Via Pipeline Balancing (Abstract)

Srilatha Manne , Compaq Computer Corporation
R. Iris Bahar , Brown University
pp. 0218

Energy-Effective Issue Logic (Abstract)

Antonio González , Universitat Polit?cnica de Catalunya
Daniele Folegnani , Universitat Polit?cnica de Catalunya
pp. 0230

Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power (Abstract)

Zhigang Hu , Princeton University
Margaret Martonosi , Princeton University
Stefanos Kaxiras , Agere Systems
pp. 0240
Session 8: Performance Tools and Evaluations

Variability in the Execution of Multimedia Applications and Implications for Architecture (Abstract)

Chanik Park , Seoul National University
Sarita V. Adve , University of Illinois at Urbana-Champaign
Jayanth Srinivasan , University of Illinois at Urbana-Champaign
Rohit Jain , University of Illinois at Urbana-Champaign
Praful Kaul , Transmeta Corporation
Christopher J. Hughes , University of Illinois at Urbana-Champaign
pp. 0254

Measuring Experimental Error in Microprocessor Simulation (Abstract)

Doug Burger , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
Rajagopalan Desikan , The University of Texas at Austin
pp. 0266

Rapid Profiling via Stratified Sampling (Abstract)

Rastislav Bodík , University of Wisconsin-Madison
James E. Smith , University of Wisconsin-Madison
S. Subramanya Sastry , University of Wisconsin-Madison
pp. 0278

Author Index (PDF)

pp. 0291
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