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Proceedings of 27th International Symposium on Computer Architecture (2000)
Vancouver, BC, Canada
June 14, 2000 to June 14, 2000
ISSN: 1063-6897
ISBN: 1-58113-232-8
TABLE OF CONTENTS

A scalable approach to thread-level speculation (Abstract)

J.G. Steffan , Dept. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 1-12

Transient fault detection via simultaneous multithreading (PDF)

S.K. Reinhardt , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 25-36

Trace preconstruction (PDF)

Q. Jacobson , Sun Microsyst., Palo Alto, CA, USA
pp. 37-46

Completion time multiple branch prediction for enhancing trace cache performance (PDF)

R. Rakvic , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 47-58

HLS: combining statistical and symbolic simulation to guide microprocessor designs (PDF)

M. Oskin , Dept. of Comput. Sci., California Univ., Davis, CA, USA
pp. 71-82

Energy-driven integrated hardware-software optimizations using SimplePower (PDF)

N. Vijaykrishnan , Microsyst. Design Lab., Pennsylvania State Univ., University Park, PA, USA
pp. 95-106

A fully associative software-managed cache design (Abstract)

E.G. Hallnor , Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
pp. 107-116

Recency-based TLB preloading (Abstract)

A. Saulsbury , Sun Microsyst. Labs., Palo Alto, CA, USA
pp. 117-127

Memory access scheduling (Abstract)

S. Rixner , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 128-138

Selective, accurate, and timely self-invalidation using last-touch prediction (Abstract)

An-Chow Lai , Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
pp. 139-148

Smart Memories: a modular reconfigurable architecture (Abstract)

K. Mai , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 161-171

Understanding the backward slices of performance degrading instructions (Abstract)

C.B. Zilles , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 172-181

On the value locality of store instructions (Abstract)

K.M. Lepak , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 182-191

Reconfigurable caches and their application to media processing (Abstract)

P. Ranganathan , Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
pp. 214-224

Circuits for wide-window superscalar processors (Abstract)

D.S. Henry , Dept. of Comput. Sci. & Electr. Eng., Yale Univ., New Haven, CT, USA
pp. 236-247

Vector instruction set support for conditional operations (PDF)

J.E. Smith , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 260-269

Instruction path coprocessors (Abstract)

Yuan Chou , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 270-281

Allowing for ILP in an embedded Java processor (PDF)

R. Radhakrishnan , Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 294-305

Multiple-banked register file architectures (PDF)

J.-L. Cruz , Dept. d'Arquitectura de Comput., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 316-325

Index of authors (PDF)

pp. 326
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