The Community for Technology Leaders
Computer Architecture, International Symposium on (1999)
Atlanta, Georgia
May 2, 1999 to May 4, 1999
ISBN: 0-7695-0170-2
TABLE OF CONTENTS

Reviewers (PDF)

pp. xii
Novel Architecture

Maps: A Compiler-Managed Memory System for Raw Machines (Abstract)

Rajeev Barua , Massachusetts Institute of Technology
Walter Lee , Massachusetts Institute of Technology
Saman Amarasinghe , Massachusetts Institute of Technology
Anant Agarwal , Massachusetts Institute of Technology
pp. 0004

Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs (Abstract)

Sriram Vajapeyam , Supercomputer Education and Research Centre and Indian Institute of Science
P.J. Joseph , Indian Institute of Science
Tulika Mitra , Indian Institute of Science
pp. 0016

PipeRench: A Coprocessor for Streaming Multimedia Acceleration (Abstract)

Seth Copen Goldstein , Carnegie Mellon University
Herman Schmit , Carnegie Mellon University
Matthew Moe , Carnegie Mellon University
Mihai Budiu , Carnegie Mellon University
Srihari Cadambi , Carnegie Mellon University
R. Reed Taylor , Carnegie Mellon University
Ronald Laufer , Carnegie Mellon University
pp. 0028
Value Prediction 1

Speculation Techniques for Improving Load Related Instruction Scheduling (Abstract)

Adi Yoaz , Intel Corporation
Mattan Erez , Intel Corporation
Ronny Ronen , Intel Corporation
Stephan Jourdan , Intel Corporation
pp. 0042

Correlated Load-Address Predictors (Abstract)

Michael Bekerman , Intel Corporation
Stephan Jourdan , Intel Corporation
Ronny Ronen , Intel Corporation
Gilad Kirshenboim , Intel Corporation
Lihu Rappoport , Intel Corporation
Adi Yoaz , Intel Corporation
Uri Weiser , Intel Corporation
pp. 0054

Selective Value Prediction (Abstract)

Brad Calder , University of California at San Diego
Glenn Reinman , University of California at San Diego
Dean M. Tullsen , University of California at San Diego
pp. 0064
Memory

Tolerating Late Memory Traps in ILP Processors (Abstract)

Xiaogang Qiu , University of Southern California
Michel Dubois , University of Southern California
pp. 0076

Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor (Abstract)

Pen-Chung Yew , University of Minnesota
Gyungho Lee , University of Texas at San Antonio
pp. 0100

Effective Jump-Pointer Prefetching for Linked Data Structures (Abstract)

Amir Roth , University of Wisconsin at Madison
Gurindar S. Sohi , University of Wisconsin at Madison
pp. 0111
Miscellaneous

A Hardware-Driven Pro_ling Scheme for Identifying Program Hot Spots to Support Runtime Optimization (Abstract)

Matthew C. Merten , University of Illinois at Urbana
Andrew R. Trick , University of Illinois at Urbana
Christopher N. George , University of Illinois at Urbana
John C. Gyllenhaal , University of Illinois at Urbana
Wen-mei W. Hwu , University of Illinois at Urbana
pp. 0136
Coherence

Is SC + ILP = RC? (Abstract)

Chris Gniady , Purdue University
Babak Falsafi , Purdue University
T.N. Vijaykumar , Purdue University
pp. 0162

Commit-Reconcile & Fences (CRF): A New Memory Model for Architects and Compiler Writers (Abstract)

Xiaowei Shen , Massachusetts Institute of Technology
Arvind , Massachusetts Institute of Technology
Larry Rudolph , Massachusetts Institute of Technology
pp. 0150

Memory Sharing Predictor: The Key to a Speculative Coherent DSM (Abstract)

An-Chow Lai , Purdue University
Babak Falsafi , Purdue University
pp. 0172
Control and ILP

Simultaneous Subordinate Microthreading (SSMT) (Abstract)

Robert S. Chappell , The University of Michigan
Jared Stark , The University of Michigan
Steven K. Reinhardt , The University of Michigan
Yale N. Patt , The University of Michigan
Sangwook P. Kim , Intel Corporation
pp. 0186

The Block-Based Trace Cache (Abstract)

Bryan Black , Carnegie Mellon University
Bohuslav Rychlik , Carnegie Mellon University
John Paul Shen , Carnegie Mellon University
pp. 0196

The Program Decision Logic Approach to Predicated Execution (Abstract)

David I. August , University of Illinois at Urbana-Champaign
John W. Sias , University of Illinois at Urbana-Champaign
Jean-Michel Puiatti , University of Illinois at Urbana-Champaign
Scott A. Mahlke , University of Illinois at Urbana-Champaign
Daniel A. Connors , University of Illinois at Urbana-Champaign
Kevin M. Crozier , University of Illinois at Urbana-Champaign
Wen-mei W. Hwu , University of Illinois at Urbana-Champaign
pp. 0208
VLSI Architecture

A Scalable Front-End Architecture for Fast Instruction Delivery (Abstract)

Glenn Reinman , University of California at San Diego
Brad Calder , University of California at San Diego
Todd Austin , Intel Corporation
pp. 0234

A Performance Comparison of Contemporary DRAM Architectures (Abstract)

Vinodh Cuppu , University of Maryland at College Park
Bruce Jacob , University of Maryland at College Park
Brian Davis , University of Michigan
Trevor Mudge , University of Michigan
pp. 0222

Area Efficient Architectures for Information Integrity in Cache Memories (Abstract)

Seongwoo Kim , Iowa State University
Arun K. Somani , Iowa State University
pp. 0246
Value Prediction 2

Value Prediction in VLIW Machines (Abstract)

Tarun Nakra , University of Pittsburgh
Rajiv Gupta , University of Pittsburgh
Mary Lou Soffa , University of Pittsburgh
pp. 0258

Storageless Value Prediction Using Prior Register Values (Abstract)

Dean M. Tullsen , University of California at San Diego
John S. Seng , University of California at San Diego
pp. 0270
Shared Memory

Multicast Snooping: A New Coherence Method Using a Multicast Address Network (Abstract)

E. Ender Bilir , University of Wisconsin-Madison
Ross M. Dickson , University of Wisconsin-Madison
Ying Hu , University of Wisconsin-Madison
Manoj Plakal , University of Wisconsin-Madison
Daniel J. Sorin , University of Wisconsin-Madison
Mark D. Hill , University of Wisconsin-Madison
David A. Wood , University of Wisconsin-Madison
pp. 0294

Index of Authors (PDF)

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