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Computer Architecture, International Symposium on (1996)
Philadelphia, Pennsylvania, United States
May 22, 1996 to May 24, 1996
ISBN: 0-89791-786-3
pp: 67
ABSTRACT
In the future, advanced integrated circuit processing and packaging technology will allow for several design options for multiprocessor microprocessors. In this paper we consider three architectures: shared-primary cache, shared-secondary cache, and shared-memory. We evaluate these three architectures using a complete system simulation environment which models the CPU, memory hierarchy and I/O devices in sufficient detail to boot and run a commercial operating system. Within our simulation environment, we measure performance using representative hand and compiler generated parallel applications, and a multiprogramming workload. Our results show that when applications exhibit fine-grained sharing, both shared-primary and shared-secondary architectures perform similarly when the full costs of sharing the primary cache are included.
INDEX TERMS
Scalable Shared Memory Multiprocessors, backward error recovery, coherence protocol, fault-tolerance
CITATION

L. Hammond, B. A. Nayfeh and K. Olukotun, "Evaluation of Design Alternatives for a Multiprocessor Microprocessor," 23rd Annual International Symposium on Computer Architecture(ISCA), Philadelphia, PA, USA, 1996, pp. 67.
doi:10.1109/ISCA.1996.10017
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