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Proceedings 22nd Annual International Symposium on Computer Architecture (1995)
Santa Margherita Ligure, Italy
June 22, 1995 to June 24, 1995
ISSN: 1063-6897
ISBN: 0-89791-698-0
TABLE OF CONTENTS

The MIT Alewife machine: architecture and performance (Abstract)

A. Agarwal , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
R. Bianchini , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
D. Chaiken , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
K.L. Johnson , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
D. Kranz , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
J. Kubiatowicz , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
Beng-Hong Lim , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
K. Mackenzie , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
D. Yeung , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
pp. 2-13

The EM-X parallel computer: architecture and basic performance (Abstract)

Y. Kodama , Electrotech. Lab., Ibaraki, Japan
H. Sakane , Electrotech. Lab., Ibaraki, Japan
M. Sato , Electrotech. Lab., Ibaraki, Japan
H. Yamana , Electrotech. Lab., Ibaraki, Japan
pp. 14-23

The SPLASH-2 programs: characterization and methodological considerations (Abstract)

S.C. Woo , Comput. Syst. Lab., Stanford Univ., CA, USA
M. Ohara , Comput. Syst. Lab., Stanford Univ., CA, USA
E. Torrie , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 24-36

Efficient strategies for software-only directory protocols in shared-memory multiprocessors (Abstract)

H. Grahn , Dept. of Comput. Eng., Lund Univ., Sweden
P. Stenstrom , Dept. of Comput. Eng., Lund Univ., Sweden
pp. 38-47

Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors (PDF)

A.R. Lebeck , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
D.A. Wood , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 48-59

Boosting the performance of hybrid snooping cache protocols (PDF)

F. Dahlgren , Dept. of Comput. Eng., Lund Univ., Sweden
pp. 60-69

S-Connect: from networks of workstations to supercomputer performance (PDF)

A.G. Nowatzyk , Sun Microsystems Comput. Corp., USA
M.C. Browne , Sun Microsystems Comput. Corp., USA
pp. 71-82

Destage algorithms for disk arrays with non-volatile caches (PDF)

A. Varma , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
Q. Jacobson , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 83-95

Evaluating multi-port frame buffer designs for a mesh-connected multicomputer (PDF)

G. Stoll , Dept. of Comput. Sci., Princeton Univ., NJ, USA
Bin Wei , Dept. of Comput. Sci., Princeton Univ., NJ, USA
D. Clark , Dept. of Comput. Sci., Princeton Univ., NJ, USA
E.W. Felten , Dept. of Comput. Sci., Princeton Univ., NJ, USA
Kai Li , Dept. of Comput. Sci., Princeton Univ., NJ, USA
pp. 96-105

Exploring configurations of functional units in an out-of-order superscalar processor (Abstract)

S. Jourdan , Inst. de Recherche en Inf., Univ. Paul Sabatier, Toulouse, France
P. Sainrat , Inst. de Recherche en Inf., Univ. Paul Sabatier, Toulouse, France
D. Litaize , Inst. de Recherche en Inf., Univ. Paul Sabatier, Toulouse, France
pp. 117-125

Unconstrained speculative execution with predicated state buffering (Abstract)

H. Ando , Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
C. Nakanishi , Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
T. Hara , Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
M. Nakaya , Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
pp. 126-137

A comparison of full and partial predicated execution support for ILP processors (Abstract)

S.A. Mahlke , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
R.E. Hank , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.E. McCormick , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
D.I. August , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
W.W. Hwu , Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
pp. 138-149

Performance evaluation of the PowerPC 620 microarchitecture (Abstract)

T.A. Diep , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
C. Nelson , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.P. Shen , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 163-174

Reducing TLB and memory overhead using online superpage promotion (Abstract)

T.H. Romer , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
W.H. Ohlrich , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
A.R. Karlin , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
B.N. Bershad , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 176-187

Speeding up irregular applications in shared-memory multiprocessors: memory binding and group prefetching (Abstract)

Zheng Zhang , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
J. Torrellas , Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
pp. 188-199

An efficient, fully adaptive deadlock recovery scheme: DISHA (Abstract)

K.V. Anjan , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
T.M. Pinkston , Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
pp. 201-210

Analysis and implementation of hybrid switching (Abstract)

K.G. Shin , Real-Time Comput. Lab., Michigan Univ., Ann Arbor, MI, USA
S.W. Daniel , Real-Time Comput. Lab., Michigan Univ., Ann Arbor, MI, USA
pp. 211-219

Configurable flow control mechanisms for fault-tolerant routing (Abstract)

Binh Vien Dao , Comput. Syst. Res. Lab., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 220-229

NIFDY: a low overhead, high throughput network interface (Abstract)

T. Callahan , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
S.C. Goldstein , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
pp. 230-241

Vector multiprocessors with arbitrated memory access (PDF)

M. Peiron , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
M. Valero , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
E. Ayguade , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 243-252

Skewed associativity enhances performance predictability (PDF)

F. Bodin , IRISA, Rennes, France
A. Seznec , IRISA, Rennes, France
pp. 265-274

A comparative analysis of schemes for correlated branch prediction (PDF)

C. Young , Div. of Appl. Sci., Harvard Univ., Cambridge, MA, USA
N. Gloy , Div. of Appl. Sci., Harvard Univ., Cambridge, MA, USA
M.D. Smith , Div. of Appl. Sci., Harvard Univ., Cambridge, MA, USA
pp. 276-286

Next cache line and set prediction (PDF)

B. Calder , Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
D. Grunwald , Dept. of Comput. Sci., Colorado Univ., Boulder, CO, USA
pp. 287-296

A comparison of architectural support for messaging in the TMC CM-5 and the Cray T3D (PDF)

V. Karamcheti , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
A.A. Chien , Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
pp. 298-307

Optimizing memory system performance for communication in parallel computers (PDF)

T. Stricker , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
T. Gross , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 308-319

Empirical evaluation of the CRAY-T3D: a compiler perspective (PDF)

R.H. Arpaci , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
D.E. Culler , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
A. Krishnamurthy , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
S.G. Steinberg , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
K. Yelick , Div. of Comput. Sci., California Univ., Berkeley, CA, USA
pp. 320-331

Optimization of instruction fetch mechanisms for high issue rates (PDF)

T.M. Conte , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
K.N. Menezes , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
P.M. Mills , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
B.A. Patel , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
pp. 333-344

Instruction fetching: Coping with code bloat (PDF)

R. Uhlig , Gesellshaft fur Math. und Datenverarbeitung, Sankt Augustin, Germany
pp. 345-356

Instruction cache fetch policies for speculative execution (PDF)

D. Lee , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
J.-L. Baer , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 357-367

Streamlining data cache access with fast address calculation (PDF)

T.M. Austin , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
D.N. Pnevmatikatos , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
G.S. Sohi , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 369-380

CAT - caching address tags - a technique for reducing area cost of on-chip caches (Abstract)

Hong Wan , Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
Tong Sun , Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
Qing Yang , Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA
pp. 381-390

Simultaneous multithreading: Maximizing on-chip parallelism (PDF)

D.M. Tullsen , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
S.J. Eggers , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
H.M. Levy , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 392-403

Architecture validation for processors (PDF)

R.C. Ho , Comput. Syst. Lab., Stanford Univ., CA, USA
C. Han Yang , Comput. Syst. Lab., Stanford Univ., CA, USA
M.A. Horowitz , Comput. Syst. Lab., Stanford Univ., CA, USA
D.L. Dill , Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 404-413

Multiscalar processors (PDF)

G.S. Sohi , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
S.E. Breach , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
T.N. Vijaykumar , Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
pp. 414-425

Index of authors (PDF)

pp. 426
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