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Parallel Processing Symposium, International (1995)
Santa Barbara, CA
Apr. 25, 1995 to Apr. 28, 1995
ISSN: 1063-7133
ISBN: 0-8186-7074-6
pp: 480
M. Marchetti , Dept. of Comput. Sci., Rochester Univ., NY, USA
L. Kontothanassis , Dept. of Comput. Sci., Rochester Univ., NY, USA
R. Bianchini , Dept. of Comput. Sci., Rochester Univ., NY, USA
M.L. Scott , Dept. of Comput. Sci., Rochester Univ., NY, USA
ABSTRACT
The cost of a cache miss depends heavily on the location of the main memory that backs the missing line. For certain applications, this cost is a major factor in overall performance. We report on the utility of OS-based page placement as a mechanism to increase the frequency with which cache fills access local memory in distributed shared memory multiprocessors. Even with the very simple policy of first-use placement, we find significant improvements over round-robin placement for many applications on both hardware- and software-coherent systems. For most of our applications, first-use placement allows 35 to 75 percent of cache fills to be performed locally, resulting in performance improvements of up to 40 percent with respect to round-robin placement. We were surprised to find no performance advantage in more sophisticated policies, including page migration and page replication. In fact, in many cases the performance of our applications suffered under these policies.
INDEX TERMS
cache storage; storage management; shared memory systems; paged storage; operating systems (computers); page placement policies; cache fills; shared-memory systems; OS-based page placement; distributed shared memory multiprocessors; performance; page migration; page replication
CITATION

L. Kontothanassis, M. Marchetti, M. Scott and R. Bianchini, "Using simple page placement policies to reduce the cost of cache fills in coherent shared-memory systems," Parallel Processing Symposium, International(IPPS), Santa Barbara, CA, 1995, pp. 480.
doi:10.1109/IPPS.1995.395974
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