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2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (2016)
Chicago, IL, USA
May 23, 2016 to May 27, 2016
ISBN: 978-1-5090-3683-7
pp: 1239-1248
ABSTRACT
Fail-stop and silent errors are omnipresent on large-scale platforms. Efficient resilience techniques must accommodate both error sources. To cope with the double challenge, a two-level checkpointing and rollback recovery approach can be used, with additional verifications for silent error detection. A fail-stop error leads to the loss of the whole memory content, hence the obligation to checkpoint on a stable storage (e.g., an external disk). On the contrary, it is possible to use in-memory checkpoints for silent errors, which provide a much smaller checkpointing and recovery overhead. Furthermore, recent detectors offer partial verification mechanisms that are less costly than the guaranteed ones but do not detect all silent errors. In this paper, we show how to combine all of these techniques for HPC applications whose dependency graph forms a linear chain. We present a sophisticated dynamic programming algorithm that returns the optimal solution in polynomial time. Simulation results demonstrate that the combined use of multi-level checkpointing and verifications leads to improved performance compared to the standard single-level checkpointing algorithm.
INDEX TERMS
Checkpointing, Heuristic algorithms, Dynamic programming, Resilience, TV, Algorithm design and analysis, Hardware
CITATION

A. Benoit, A. Cavelan, Y. Robert and H. Sun, "Two-Level Checkpointing and Verifications for Linear Task Graphs," 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Chicago, IL, USA, 2016, pp. 1239-1248.
doi:10.1109/IPDPSW.2016.106
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