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2015 IEEE International Parallel and Distributed Processing Symposium Workshop (IPDPSW) (2015)
Hyderabad, India
May 25, 2015 to May 29, 2015
ISBN: 978-1-4673-7684-6
pp: 182-189
ABSTRACT
Process Networks (PNs)-based models of computation have proven as a successful framework for describing multiple kinds of applications in the Reconfigurable Hardware (RH) domain. Due to their intrinsically parallel and reactive behavior, and well-known techniques to automatically manipulate some of their instances, they are very amenable to FPGAs. One problem associated with PNs is that the number of nodes is usually proportional with the parallel portions of computation, and a tool to automatically map tasks to FPGAs is required when multiple FPGAs are employed to improve performance (via increased parallelism). While it is possible to solve this problem in an exact manner via dynamic programming approaches, this is not the case when practical graphs are under examination, i.e. Graphs with potentially thousands nodes. In this work we extend a well-known graph partitioning technique, namely Multi-Level K-ways partitioning algorithm, in order to cope with such scenario.
INDEX TERMS
Partitioning algorithms, Bandwidth, Field programmable gate arrays, Approximation algorithms, Heuristic algorithms, Clustering algorithms, Resource management
CITATION

R. Cattaneo, M. B. Moradmand, D. Sciuto and M. D. Santambrogio, "K-Ways Partitioning of Polyhedral Process Networks: A Multi-level Approach," 2015 IEEE International Parallel and Distributed Processing Symposium Workshop (IPDPSW), Hyderabad, India, 2015, pp. 182-189.
doi:10.1109/IPDPSW.2015.17
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