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2015 IEEE International Parallel and Distributed Processing Symposium Workshop (IPDPSW) (2015)
Hyderabad, India
May 25, 2015 to May 29, 2015
ISBN: 978-1-4673-7684-6
pp: 97-104
ABSTRACT
Within this paper we present a floor planner for partially-reconfigurable FPGAs that allow the designer to consider bit stream relocation constraints during the design of the system. The presented approach is an extension of our previous work on floor planning based on a Mixed-Integer Linear Programming (MILP) formulation, thus allowing the designer to optimize a set of different metrics within a user defined objective function while considering preferences related directly to relocation capabilities. Experimental results shows that the presented approach is able to reserve multiple free areas for a reconfigurable region with a small impact on the solution cost in terms of wire length and size of the configuration data.
INDEX TERMS
Field programmable gate arrays, Measurement, Context, Shape, Linear programming, Semantics, Tiles
CITATION

M. Rabozzi, R. Cattaneo, T. Becker, W. Luk and M. D. Santambrogio, "Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems," 2015 IEEE International Parallel and Distributed Processing Symposium Workshop (IPDPSW), Hyderabad, India, 2015, pp. 97-104.
doi:10.1109/IPDPSW.2015.52
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