2014 IEEE International Parallel & Distributed Processing Symposium Workshops (IPDPSW) (2014)
Phoenix, AZ, USA
May 19, 2014 to May 23, 2014
Harnessing the full capabilities offered by reconfigurable hardware is still a demanding task: the lack of proper methodologies and the intrinsic time consuming and error prone tailoring of these systems around the specific application places a barrier to the adoption of this technology. Partial and Dynamic Reconfiguration (PDR), in this context, is a specific feature whose potential is undiscussed but yet to uncover. In this work, we propose PaRA-Sched, an improvement for a state of the art, highly automated design methodology that allows the designer to rapidly explore the impact of PDR employment during the early stages of the design process. Specifically, we extend the scheduling infrastructure of the framework to explicitly take into account PDR to better explore the design space and improve overall performance by automatically masking reconfiguration time when possible. We show how this additional degree of freedom leads to designs whose performance are improved with respect to the baseline, with a limited increase in time spent during DSE.
Scheduling, Heuristic algorithms, Program processors, Field programmable gate arrays, Algorithm design and analysis, Processor scheduling, Hardware
R. Cattaneo, R. Bellini, G. Durelli, C. Pilato, M. D. Santambrogio and D. Sciuto, "PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures," 2014 IEEE International Parallel & Distributed Processing Symposium Workshops (IPDPSW), Phoenix, AZ, USA, 2014, pp. 243-250.