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2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (2013)
Cambridge, MA, USA USA
May 20, 2013 to May 24, 2013
pp: 252-259
ABSTRACT
This paper targets the time-consuming problem of user IOs and debugging in MPSoC. It introduces the concept of dynamic allocation of virtual UARTs to implement standard-IOs in various hardware and software contexts, on a hybrid FPGA. It discusses the advantages and limitations of this abstraction, presents an implementation on the hybrid Xilinx Zynq device. Multiple experiences illustrate how hardware (processors) and software heterogeneities can be handled. As a result, a real MJPEG decoder is debugged and validated in a couple of hours thanks to standard-IOs and virtual UARTs.
INDEX TERMS
Zynq, standard-IOs, virtual UART, runtime service, heterogeneous multi-processors, micro-blaze,
CITATION
Pierre Bomel, Kevin Martin, Jean-Philippe Diguet, "Virtual UARTs for Reconfigurable Multi-processor Architectures", 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, vol. 00, no. , pp. 252-259, 2013, doi:10.1109/IPDPSW.2013.25
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