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2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (2013)
Cambridge, MA, USA USA
May 20, 2013 to May 24, 2013
pp: 202-211
Programmable hardware built on a regular architecture can be used to address the challenges associated with using many fixed core architectures for applications which have varying compute power requirements during the lifetime of execution. The fine granularity of FPGAs is however unsuitable for effectively exploiting runtime reconfiguration because of the high overheads involved. Effective use of a dynamically reconfigurable fabric across a range of applications remains a challenge. In this work, we use a model coarse grain reconfigurable fabric to explore the potential of such a fabric for a range of key reconfiguration parameters. This coarse grain reconfigurable array with malleable communication links is used for design space exploration of two compute intensive kernel implementations which exploit dynamically reconfiguration. The semi-systolic near neighbour communication interconnect can be dynamically reconfigured for each "epoch" of computation. Different blocks of the application program reuse the compute grain in different epochs. Some of the links between the compute tiles are changed during the reconfiguration phase and because the architecture is partially reconfigured, the reconfiguration in some tiles can be completely overlapped with computation in other tiles. The paper proposes a methodology to exploit this design paradigm to drastically reduce the context switch overhead for rebalancing the pipeline to build high performance/area applications on this fabric.
JPEG encoder, Dynamic Reconfiguration, CGRA, FFT,
Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan, "Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs", 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, vol. 00, no. , pp. 202-211, 2013, doi:10.1109/IPDPSW.2013.121
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