2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (2012)
Shanghai, China China
May 21, 2012 to May 25, 2012
Performance estimation of an application on any processor is becoming a essential task, specially when the processor is used for high performance computing. Our work here presents a model to estimate performance of various applications on a modern GPU. Recently, GPUs are getting popular in the area of high performance computing along with original application domain of graphics. We have chosen FERMI architecture from NVIDIA, as an example of modern GPU. Our work is divided into two basic parts, first we try to estimate computation time and then follow it up with estimation of memory access time. Instructions in the kernel contribute significantly to the computation time. We have developed a model to count the number of instructions in the kernel. We have found our instruction count methodology to give exact count. Memory access time is calculated in three steps, address trace generation, cache simulation and average memory latency per warp. Finally, computation time is combined with memory access time to predict the total execution time. This model has been tested with micro-benchmarks as well as real life kernels like blowfish encryption. matrix multiplication and image smoothing. We have found that our average estimation errors for these applications range from-7.76% to 55%.
Graphics processing unit, Kernel, Computer architecture, Estimation, Equations, Clocks, Computational modeling, blocks, performance, estimation, prediction, FERMI GPU, address trace, instruction count, cache, memory, warp, threads
Arun Kumar Parakh, M. Balakrishnan, Kolin Paul, "Performance Estimation of GPUs with Cache", 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, vol. 00, no. , pp. 2384-2393, 2012, doi:10.1109/IPDPSW.2012.328