The Community for Technology Leaders
2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW) (2010)
Atlanta, GA, USA
Apr. 19, 2010 to Apr. 23, 2010
ISBN: 978-1-4244-6533-0
pp: 1-8
Yang Ding , CSE Department, Pennsylvania State University, USA
Mahmut Kandemir , CSE Department, Pennsylvania State University, USA
Mary Jane Irwin , CSE Department, Pennsylvania State University, USA
Padma Raghavan , CSE Department, Pennsylvania State University, USA
ABSTRACT
Chip multiprocessors (CMPs) are expected to dominate the landscape of computer architecture in the near future. The potential performance gains that can be achieved by the use of CMPs depend, to a large extent, on how much parallelism can be extracted from applications. One effective way of utilizing CMP architectures is to execute multiple (potentially multi-threaded) applications at the same time. In this work, we propose and evaluate a dynamic (runtime) core partitioning scheme for CMPs that exploits application level information. Focusing on an optimization metric called the weighted energy-delay product gain (W-EDPG), we dynamically partition available cores across competing applications during the course of execution. This dynamic partitioning uses input from a curve fitting model to predict the best operating points for an application at runtime. It can generate nonuniform core allocations across applications (i.e., some applications may have more or fewer cores than others) if doing so increases the value of the W-EDPG metric. We compare this approach against several alternative schemes (including equal partitioning of cores and standard operating system based scheduling). Our experiments indicate that the proposed core partitioning scheme improves the W-EDPG metric significantly (e.g., 14.0% on average over the equal partitioning scheme on a 16-core CMP when four multi-threaded applications are executing concurrently).
INDEX TERMS
CITATION

M. Kandemir, P. Raghavan, M. J. Irwin and Y. Ding, "Dynamic core partitioning for energy efficiency," 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), Atlanta, GA, USA, 2010, pp. 1-8.
doi:10.1109/IPDPSW.2010.5470909
94 ms
(Ver 3.3 (11022016))